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IDT71V2576S166PF8 PDF预览

IDT71V2576S166PF8

更新时间: 2023-07-15 00:00:00
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
20页 359K
描述
Cache SRAM, 128KX36, 3.5ns, CMOS, PQFP100, PLASTIC, TQFP-100

IDT71V2576S166PF8 数据手册

 浏览型号IDT71V2576S166PF8的Datasheet PDF文件第2页浏览型号IDT71V2576S166PF8的Datasheet PDF文件第3页浏览型号IDT71V2576S166PF8的Datasheet PDF文件第4页浏览型号IDT71V2576S166PF8的Datasheet PDF文件第5页浏览型号IDT71V2576S166PF8的Datasheet PDF文件第6页浏览型号IDT71V2576S166PF8的Datasheet PDF文件第7页 
128K X 36, 256K X 18  
3.3V Sychronous SRAMs  
2.5V I/O, Pipelined Outputs,  
Burst Counter, Single Cycle Deselect  
Preliminary  
IDT71V2576  
IDT71V2578  
Features  
Description  
128K x 36, 256K x 18 memory configurations  
The IDT71V2576/78 are high-speed SRAMs organized as 128K x  
36/256Kx18.TheIDT71V2576/78SRAMscontainwrite,data,address  
andcontrolregisters. InternallogicallowstheSRAMtogenerateaself-  
timedwritebaseduponadecisionwhichcanbeleftuntiltheendofthewrite  
cycle.  
Supports high system speed:  
– 200MHz 3.1ns clock access time  
– 183MHz 3.3ns clock access time  
– 166MHz 3.5ns clock access time  
– 150MHz 3.8ns clock access time  
– 133MHz 4.2ns clock access time  
Theburstmodefeatureoffersthehighestlevelofperformancetothe  
systemdesigner,astheIDT71V2576/78canprovidefourcyclesofdata  
forasingleaddresspresentedtotheSRAM. Aninternalburstaddress  
LBO input selects interleaved or linear burst mode  
Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe  
enable (BWE), and byte writes (BWx)  
3.3V core power supply  
Power down controlled by ZZ input  
2.5V I/O  
accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone  
cycle before it is available on the next rising clock edge. If burst mode  
operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput  
datawillbeavailabletotheuseronthenextthreerisingclockedges. The  
Packaged in a JEDEC Standard 100-lead plastic thin quad orderofthesethreeaddressesaredefinedbytheinternalburstcounter  
flatpack (TQFP) and 119-lead ball grid array (BGA)  
and the LBOinput pin.  
The IDT71V2576/78 SRAMs utilize IDT’s latest high-performance  
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm  
100-leadthinplasticquadflatpack(TQFP)aswellasa119-leadballgrid  
array (BGA).  
PinDescriptionSummary  
0
17  
A -A  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enable  
CE  
0
1
CS , CS  
Chip Selects  
Output Enable  
OE  
Global Write Enable  
Byte Write Enable  
Individual Byte Write Selects  
Clock  
GW  
BWE  
(1)  
1,  
2,  
3,  
4
BW BW BW BW  
CLK  
ADV  
ADSC  
ADSP  
LBO  
ZZ  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Sleep Mode  
Synchronous  
Synchronous  
Synchronous  
DC  
Asynchronous  
Synchronous  
N/A  
0
31  
P1  
P4  
I/O -I/O , I/O -I/O  
Data Input / Output  
Core Power, I/O Power  
Ground  
DD DDQ  
V
V
, V  
Supply  
Supply  
SS  
N/A  
4876 tbl 01  
NOTE:  
1. BW3 and BW4 are not applicable for the IDT71V2578.  
SEPTEMBER1999  
1
©1999 Integrated Device Technology, Inc.  
DSC-4876/5  

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