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IDT71421SA25LG PDF预览

IDT71421SA25LG

更新时间: 2024-11-05 13:08:39
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
16页 255K
描述
Multi-Port SRAM, 2KX8, 25ns, CMOS, CQCC52, HERMETIC SEALED, LCC-52

IDT71421SA25LG 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:LCC
包装说明:QCCN,针数:52
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.53
Is Samacsys:N最长访问时间:25 ns
其他特性:INTERRUPT FLAG; AUTOMATIC POWER-DOWNJESD-30 代码:S-CQCC-N52
JESD-609代码:e3长度:19.05 mm
内存密度:16384 bit内存集成电路类型:MULTI-PORT SRAM
内存宽度:8功能数量:1
端口数量:2端子数量:52
字数:2048 words字数代码:2000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:2KX8
输出特性:3-STATE可输出:YES
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QCCN
封装形状:SQUARE封装形式:CHIP CARRIER
并行/串行:PARALLEL峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:2.2098 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:NO LEAD
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:19.05 mm
Base Number Matches:1

IDT71421SA25LG 数据手册

 浏览型号IDT71421SA25LG的Datasheet PDF文件第2页浏览型号IDT71421SA25LG的Datasheet PDF文件第3页浏览型号IDT71421SA25LG的Datasheet PDF文件第4页浏览型号IDT71421SA25LG的Datasheet PDF文件第5页浏览型号IDT71421SA25LG的Datasheet PDF文件第6页浏览型号IDT71421SA25LG的Datasheet PDF文件第7页 
IDT7132SA/LA  
IDT7142SA/LA  
HIGH SPEED  
2K x 8 DUAL PORT  
STATIC RAM  
MASTERIDT7132easilyexpandsdatabuswidthto16-or-more  
bits using SLAVE IDT7142  
Features  
High-speed access  
On-chip port arbitration logic (IDT7132 only)  
BUSY output flag on IDT7132; BUSY input on IDT7142  
Battery backup operation —2V data retention (LA only)  
TTL-compatible, single 5V ±10% power supply  
Available in 48-pin DIP, LCC and Flatpack, and 52-pin PLCC  
packages  
Military product compliant to MIL-PRF-38535 QML  
Industrial temperature range (–40°C to +85°C) is available for  
selected speeds  
– Commercial:20/25/35/55/100ns(max.)  
– Industrial: 25ns (max.)  
– Military:25/35/55/100ns(max.)  
Low-power operation  
IDT7132/42SA  
Active: 325mW (typ.)  
Standby: 5mW (typ.)  
– IDT7132/42LA  
Active:325mW(typ.)  
Standby: 1mW (typ.)  
Functional Block Diagram  
OER  
OEL  
CEL  
CER  
R/W  
L
R/WR  
I/OOL-I/O7L  
I/OOR-I/O7R  
I/O  
Control  
I/O  
Control  
m
(1,2)  
(1,2)  
BUSY  
L
BUSY  
R
A
10L  
A
10R  
0R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
0L  
A
11  
11  
ARBITRATION  
LOGIC  
CE  
OE  
R
R
CE  
OE  
L
L
R/WR  
R/W  
L
2692 drw 01  
NOTES:  
1. IDT7132 (MASTER): BUSY is open drain output and requires pullup resistor of 270.  
IDT7142 (SLAVE): BUSY is input.  
2. Open drain output: requires pullup resistor of 270.  
JUNE 2004  
1
DSC-2692/16  
©2004IntegratedDeviceTechnology,Inc.  

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