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IDT71342LA20JG

更新时间： 2024-11-26 13:08:39
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
13页 147K
描述
Dual-Port SRAM, 4KX8, 20ns, CMOS, PQCC52, PLASTIC, LCC-52

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IDT71342LA20JG 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：LCC
包装说明：QCCJ,针数：52
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.41风险等级：5.45
Is Samacsys：N最长访问时间：20 ns
其他特性：SEMAPHORE; AUTOMATIC POWER-DOWN; BATTERY BACKUPJESD-30 代码：S-PQCC-J52
JESD-609代码：e3长度：19.1262 mm
内存密度：32768 bit内存集成电路类型：DUAL-PORT SRAM
内存宽度：8功能数量：1
端口数量：2端子数量：52
字数：4096 words字数代码：4000
工作模式：ASYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：4KX8
输出特性：3-STATE可输出：YES
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装形状：SQUARE封装形式：CHIP CARRIER
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：4.57 mm
最小待机电流：2 V最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Matte Tin (Sn)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：19.1262 mmBase Number Matches：1

IDT71342LA20JG 数据手册

 浏览型号IDT71342LA20JG的Datasheet PDF文件第2页浏览型号IDT71342LA20JG的Datasheet PDF文件第3页浏览型号IDT71342LA20JG的Datasheet PDF文件第4页浏览型号IDT71342LA20JG的Datasheet PDF文件第5页浏览型号IDT71342LA20JG的Datasheet PDF文件第6页浏览型号IDT71342LA20JG的Datasheet PDF文件第7页 
IDT71342SA/LA  
HIGH-SPEED  
4K x 8 DUAL-PORT  
STATIC RAM WITH SEMAPHORE  
Integrated Device Technology, Inc.  
FEATURES:  
DESCRIPTION:  
• High-speed access  
TheIDT71342isanextremelyhigh-speed4Kx8Dual-Port  
Static RAM with full on-chip hardware support of semaphore  
signalling between the two ports.  
— Commercial: 20/25/35/45/55/70ns (max.)  
• Low-power operation  
— IDT71342SA  
TheIDT71342providestwoindependentportswithseparate  
control, address, and I/O pins that permit independent,  
asynchronous access for reads or writes to any location in  
memory. To assist in arbitrating between ports, a fully  
independent semaphore logic block is provided. This block  
contains unassigned flags which can be accessed by either  
side; however, only one side can control the flag at any time.  
Active: 500mW (typ.)  
Standby: 5mW (typ.)  
— IDT71342LA  
Active: 500mW (typ.)  
Standby: 1mW (typ.)  
• Fully asynchronous operation from either port  
• Full on-chip hardware support of semaphore signalling An automatic power down feature, controlled by CEand SEM,  
between ports  
permits the on-chip circuitry of each port to enter a very low  
standby power mode (both CE and SEM High).  
• Battery backup operation—2V data retention  
• TTL-compatible; single 5V (±10%) power supply  
• Available in plastic packages  
• Industrial temperature range (–40°C to +85°C) is avail-  
able, tested to military electrical specifications  
Fabricated using IDT’s CMOS high-performance  
technology, this device typically operates on only 500mW of  
power. Low-power (LA) versions offer battery backup data  
retentioncapability,witheachporttypicallyconsuming200µW  
from a 2V battery. The device is packaged in either a 64-pin  
TQFP, thin quad plastic flatpack, or a 52-pin PLCC.  
FUNCTIONAL BLOCK DIAGRAM  
R/  
WL  
R/  
WR  
CER  
CEL  
OER  
OEL  
COLUMN  
I/O  
COLUMN  
I/O  
I/O0R - I/O7R  
I/O0L- I/O7L  
MEMORY  
ARRAY  
SEMAPHORE  
LOGIC  
SEM  
R
SEM  
L
LEFT SIDE  
ADDRESS  
DECODE  
LOGIC  
RIGHT SIDE  
ADDRESS  
DECODE  
LOGIC  
A
0R- A11R  
A0L- A11L  
2721 drw 01  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
COMMERCIAL TEMPERATURE RANGE  
OCTOBER 1996  
©1996 Integrated Device Technology, Inc.  
DSC-2721/4  
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.  
1
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IDT71342LA25J8 IDT

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