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IDT7132LA100L48GB PDF预览

IDT7132LA100L48GB

更新时间: 2024-09-29 13:08:39
品牌 Logo 应用领域
艾迪悌 - IDT 存储内存集成电路静态存储器
页数 文件大小 规格书
11页 176K
描述
Dual-Port SRAM, 2KX8, 100ns, CMOS, CQCC48, 0.570 X 0.570 INCH, 0.680 INCH HEIGHT, GREEN, MS-009-AF, LCC-48

IDT7132LA100L48GB 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:LCC
包装说明:QCCN, LCC48,.56SQ,40针数:48
Reach Compliance Code:compliantECCN代码:3A001.A.2.C
HTS代码:8542.32.00.41风险等级:5.23
最长访问时间:100 ns其他特性:AUTOMATIC POWER DOWN
I/O 类型:COMMONJESD-30 代码:S-CQCC-N48
JESD-609代码:e3长度:14.3002 mm
内存密度:16384 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:8功能数量:1
端口数量:2端子数量:48
字数:2048 words字数代码:2000
工作模式:ASYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:2KX8
输出特性:3-STATE封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:QCCN封装等效代码:LCC48,.56SQ,40
封装形状:SQUARE封装形式:CHIP CARRIER
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:5 V认证状态:Not Qualified
筛选级别:MIL-PRF-38535座面最大高度:3.048 mm
最大待机电流:0.004 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.14 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:MATTE TIN端子形式:NO LEAD
端子节距:1.016 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:14.3002 mm
Base Number Matches:1

IDT7132LA100L48GB 数据手册

 浏览型号IDT7132LA100L48GB的Datasheet PDF文件第2页浏览型号IDT7132LA100L48GB的Datasheet PDF文件第3页浏览型号IDT7132LA100L48GB的Datasheet PDF文件第4页浏览型号IDT7132LA100L48GB的Datasheet PDF文件第5页浏览型号IDT7132LA100L48GB的Datasheet PDF文件第6页浏览型号IDT7132LA100L48GB的Datasheet PDF文件第7页 
IDT7132SA/LA  
IDT7142SA/LA  
HIGH-SPEED  
2K x 8 DUAL-PORT  
STATIC RAM  
Integrated Device Technology, Inc.  
FEATURES:  
DESCRIPTION:  
• High-speed access  
The IDT7132/IDT7142 are high-speed 2K x 8 Dual-Port  
Static RAMs. The IDT7132 is designed to be used as a stand-  
alone 8-bit Dual-Port RAM or as a “MASTER” Dual-Port RAM  
together with the IDT7142 “SLAVE” Dual-Port in 16-bit-or-  
more word width systems. Using the IDT MASTER/SLAVE  
Dual-Port RAM approach in 16-or-more-bit memory system  
applications results in full-speed, error-free operation without  
the need for additional discrete logic.  
— Military: 25/35/55/100ns (max.)  
— Commercial: 25/35/55/100ns (max.)  
— Commercial: 20ns only in PLCC for 7132  
• Low-power operation  
— IDT7132/42SA  
Active: 550mW (typ.)  
Standby: 5mW (typ.)  
— IDT7132/42LA  
Both devices provide two independent ports with separate  
control, address, and l/O pins that permit independent, asyn-  
chronousaccessforreadsorwritestoanylocationinmemory.  
An automatic power down feature, controlled by CE permits  
Active: 550mW (typ.)  
Standby: 1mW (typ.)  
• Fully asynchronous operation from either port  
• MASTER IDT7132 easily expands data bus width to 16-or- the on-chip circuitry of each port to enter a very low standby  
more bits using SLAVE IDT7142  
power mode.  
• On-chip port arbitration logic (IDT7132 only)  
• BUSY output flag on IDT7132; BUSY input on IDT7142  
• Battery backup operation —2V data retention  
• TTL-compatible, single 5V ±10% power supply  
• Available in popular hermetic and plastic packages  
• Military product compliant to MIL-STD, Class B  
• Standard Military Drawing # 5962-87002  
Fabricated using IDT’s CMOS high-performance technol-  
ogy, these devices typically operate on only 550mW of power.  
Low-power (LA) versions offer battery backup data retention  
capability, with each Dual-Port typically consuming 200µW  
from a 2V battery.  
The IDT7132/7142 devices are packaged in a 48-pin  
sidebraze or plastic DIPs, 48-pin LCCs, 52-pin PLCCs, and  
• Industrial temperature range (–40°C to +85°C) is available, 48-lead flatpacks. Military grade product is manufactured in  
tested to miliary electrical specifications  
compliance with the latest revision of MIL-STD-883, Class B,  
making it ideally suited to military temperature applications  
demanding the highest level of performance and reliability.  
FUNCTIONAL BLOCK DIAGRAM  
OER  
OEL  
CE  
L
CE  
R
R/WR  
R/W  
L
I/O0L- I/O7L  
I/O0R-I/O7R  
(1,2)  
I/O  
Control  
I/O  
Control  
BUSY (1,2)  
L
BUSY  
R
A
10L  
0L  
A
A
10R  
0R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
11  
11  
NOTES:  
1. IDT7132 (MASTER): BUSY is open  
drain output and requires pullup  
resistor of 270.  
ARBITRATION  
LOGIC  
CEL  
CER  
IDT7142 (SLAVE): BUSY is input.  
2. Open drain output: requires pullup  
resistor of 270.  
2692 drw 01  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
OCTOBER 1996  
©1996 Integrated Device Technology, Inc.  
DSC-2692/8  
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.  
6.02  
1

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