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IDT71321LA45J PDF预览

IDT71321LA45J

更新时间: 2024-11-03 23:01:11
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
16页 255K
描述
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS

IDT71321LA45J 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:LCC
包装说明:PLASTIC, LCC-52针数:52
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.69
最长访问时间:45 ns其他特性:INTERRUPT FLAG; ARBITER
I/O 类型:COMMONJESD-30 代码:S-PQCC-J52
JESD-609代码:e0长度:19.1262 mm
内存密度:16384 bit内存集成电路类型:MULTI-PORT SRAM
内存宽度:8湿度敏感等级:3
功能数量:1端口数量:2
端子数量:52字数:2048 words
字数代码:2000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:2KX8输出特性:3-STATE
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC52,.8SQ
封装形状:SQUARE封装形式:CHIP CARRIER
并行/串行:PARALLEL峰值回流温度(摄氏度):225
电源:5 V认证状态:Not Qualified
座面最大高度:4.572 mm最大待机电流:0.0015 A
最小待机电流:2 V子类别:SRAMs
最大压摆率:0.145 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:19.1262 mmBase Number Matches:1

IDT71321LA45J 数据手册

 浏览型号IDT71321LA45J的Datasheet PDF文件第2页浏览型号IDT71321LA45J的Datasheet PDF文件第3页浏览型号IDT71321LA45J的Datasheet PDF文件第4页浏览型号IDT71321LA45J的Datasheet PDF文件第5页浏览型号IDT71321LA45J的Datasheet PDF文件第6页浏览型号IDT71321LA45J的Datasheet PDF文件第7页 
IDT7132SA/LA  
IDT7142SA/LA  
HIGH SPEED  
2K x 8 DUAL PORT  
STATIC RAM  
MASTERIDT7132easilyexpandsdatabuswidthto16-or-more  
bits using SLAVE IDT7142  
Features  
High-speed access  
On-chip port arbitration logic (IDT7132 only)  
BUSY output flag on IDT7132; BUSY input on IDT7142  
Battery backup operation —2V data retention (LA only)  
TTL-compatible, single 5V ±10% power supply  
Available in 48-pin DIP, LCC and Flatpack, and 52-pin PLCC  
packages  
Military product compliant to MIL-PRF-38535 QML  
Industrial temperature range (–40°C to +85°C) is available for  
selected speeds  
– Commercial:20/25/35/55/100ns(max.)  
– Industrial: 25ns (max.)  
– Military:25/35/55/100ns(max.)  
Low-power operation  
IDT7132/42SA  
Active: 325mW (typ.)  
Standby: 5mW (typ.)  
– IDT7132/42LA  
Active:325mW(typ.)  
Standby: 1mW (typ.)  
Functional Block Diagram  
OER  
OEL  
CEL  
CER  
R/W  
L
R/WR  
I/OOL-I/O7L  
I/OOR-I/O7R  
I/O  
Control  
I/O  
Control  
m
(1,2)  
(1,2)  
BUSY  
L
BUSY  
R
A
10L  
A
10R  
0R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
0L  
A
11  
11  
ARBITRATION  
LOGIC  
CE  
OE  
R
R
CE  
OE  
L
L
R/WR  
R/W  
L
2692 drw 01  
NOTES:  
1. IDT7132 (MASTER): BUSY is open drain output and requires pullup resistor of 270.  
IDT7142 (SLAVE): BUSY is input.  
2. Open drain output: requires pullup resistor of 270.  
JUNE 2004  
1
DSC-2692/16  
©2004IntegratedDeviceTechnology,Inc.  

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