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IDT7130LA55CG PDF预览

IDT7130LA55CG

更新时间: 2024-11-11 05:22:35
品牌 Logo 应用领域
艾迪悌 - IDT 存储内存集成电路静态存储器
页数 文件大小 规格书
19页 155K
描述
HIGH SPEED 1K X 8 DUAL-PORT STATIC SRAM

IDT7130LA55CG 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:DIP
包装说明:DIP, DIP48,.6针数:48
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.04
Is Samacsys:N最长访问时间:55 ns
I/O 类型:COMMONJESD-30 代码:R-CDIP-T48
JESD-609代码:e3长度:60.96 mm
内存密度:8192 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:8功能数量:1
端口数量:2端子数量:48
字数:1024 words字数代码:1000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:1KX8
输出特性:3-STATE封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DIP封装等效代码:DIP48,.6
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:PARALLEL峰值回流温度(摄氏度):225
电源:5 V认证状态:Not Qualified
座面最大高度:4.826 mm最大待机电流:0.0015 A
最小待机电流:2 V子类别:SRAMs
最大压摆率:0.11 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
宽度:15.24 mmBase Number Matches:1

IDT7130LA55CG 数据手册

 浏览型号IDT7130LA55CG的Datasheet PDF文件第2页浏览型号IDT7130LA55CG的Datasheet PDF文件第3页浏览型号IDT7130LA55CG的Datasheet PDF文件第4页浏览型号IDT7130LA55CG的Datasheet PDF文件第5页浏览型号IDT7130LA55CG的Datasheet PDF文件第6页浏览型号IDT7130LA55CG的Datasheet PDF文件第7页 
IDT7130SA/LA  
IDT7140SA/LA  
HIGH SPEED  
1K X 8 DUAL-PORT  
STATIC SRAM  
Features  
On-chip port arbitration logic (IDT7130 Only)  
High-speed access  
BUSY output flag on IDT7130; BUSY input on IDT7140  
INT flag for port-to-port communication  
– Commercial: 20/25/35/55/100ns (max.)  
Industrial: 25/55/100ns (max.)  
Military: 25/35/55/100ns (max.)  
Fully asynchronous operation from either port  
Battery backup operation–2V data retention (LA only)  
TTL-compatible, single 5V ±10% power supply  
Military product compliant to MIL-PRF-38535 QML  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Available in 48-pin DIP, LCC and Ceramic Flatpack, 52-pin  
PLCC, and 64-pin STQFP and TQFP  
Green parts available, see ordering information  
Low-power operation  
IDT7130/IDT7140SA  
Active: 550mW (typ.)  
Standby: 5mW (typ.)  
IDT7130/IDT7140LA  
Active: 550mW (typ.)  
Standby: 1mW (typ.)  
MASTER IDT7130 easily expands data bus width to 16-or-  
more-bits using SLAVE IDT7140  
Functional Block Diagram  
OER  
OEL  
CE  
R/W  
L
CE  
R/W  
R
L
R
,
I/O0L- I/O7L  
I/O0R-I/O7R  
(1,2)  
I/O  
Control  
I/O  
Control  
(1,2)  
BUSY  
L
BUSYR  
A
9L  
0L  
A
9R  
0R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
A
10  
10  
ARBITRATION  
and  
INTERRUPT  
LOGIC  
CE  
L
CE  
OE  
R/W  
R
R
OEL  
L
R
R/W  
(2)  
(2)  
INT  
R
INTL  
2689 drw 01  
NOTES:  
1. IDT7130 (MASTER): BUSY is open drain output and requires pullup resistor.  
IDT7140 (SLAVE): BUSY is input.  
2. Open drain output: requires pullup resistor.  
APRIL 2006  
1
DSC-2689/13  
©2006IntegratedDeviceTechnology,Inc.  

IDT7130LA55CG 替代型号

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