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IDT71256S35L32B PDF预览

IDT71256S35L32B

更新时间: 2024-11-19 21:19:07
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
10页 105K
描述
Standard SRAM, 32KX8, 35ns, CMOS, CQCC32, LCC-32

IDT71256S35L32B 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFJ包装说明:LCC-32
针数:32Reach Compliance Code:not_compliant
ECCN代码:3A001.A.2.CHTS代码:8542.32.00.41
风险等级:5.12最长访问时间:35 ns
I/O 类型:COMMONJESD-30 代码:R-CQCC-N32
JESD-609代码:e0长度:13.97 mm
内存密度:262144 bit内存集成电路类型:STANDARD SRAM
内存宽度:8功能数量:1
端口数量:1端子数量:32
字数:32768 words字数代码:32000
工作模式:ASYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:32KX8
输出特性:3-STATE可输出:YES
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QCCN
封装等效代码:LCC32,.45X.55封装形状:RECTANGULAR
封装形式:CHIP CARRIER并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:5 V
认证状态:Not Qualified筛选级别:MIL-STD-883 Class B
座面最大高度:3.048 mm最大待机电流:0.02 A
最小待机电流:4.5 V子类别:SRAMs
最大压摆率:0.165 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:11.43 mmBase Number Matches:1

IDT71256S35L32B 数据手册

 浏览型号IDT71256S35L32B的Datasheet PDF文件第2页浏览型号IDT71256S35L32B的Datasheet PDF文件第3页浏览型号IDT71256S35L32B的Datasheet PDF文件第4页浏览型号IDT71256S35L32B的Datasheet PDF文件第5页浏览型号IDT71256S35L32B的Datasheet PDF文件第6页浏览型号IDT71256S35L32B的Datasheet PDF文件第7页 
CMOS Static RAM  
256K (32K x 8-Bit)  
IDT71256S  
IDT71256L  
Features  
Description  
TheIDT71256isa262,144-bithigh-speedstaticRAMorganizedas  
32K x 8. It is fabricated using IDT's high-performance, high-reliability  
CMOStechnology.  
High-speed address/chip select time  
Military:25/35/45/55/70/85/100ns (max.)  
Industrial:25/35ns (max.)  
Address access times as fast as 20ns are available with power  
consumptionofonly350mW(typ.).Thecircuitalsooffersareducedpower  
standbymode.WhenCSgoesHIGH,thecircuitwillautomaticallygotoand  
remain in, a low-power standby mode as long as CSremains HIGH. In  
thefullstandbymode,thelow-powerdeviceconsumeslessthan15µW,  
typically. This capability provides significant system level power and  
coolingsavings.Thelow-power(L)versionalsooffersabatterybackup  
dataretentioncapabilitywherethecircuittypicallyconsumesonly5µW  
whenoperatingoffa2Vbattery.  
– Commercial:20/25/35ns (max.)lowpoweronly  
Low-power operation  
Battery Backup operation – 2V data retention  
Produced with advanced high-performance CMOS  
technology  
Input and output directly TTL-compatible  
Available in standard 28-pin (300 or 600 mil) ceramic DIP,  
28-pin (600 mil) plastic DIP, 28-pin (300 mil) SOJ and  
32-pin LCC  
TheIDT71256ispackagedina28-pin(300or600mil)ceramicDIP,  
a 28-pin 300 mil SOJ, a 28-pin (600 mil) plastic DIP, and a 32-pin LCC  
providinghighboardlevelpackingdensities.  
Military product compliant to MIL-STD-883, Class B  
TheIDT71256militaryRAMismanufacturedincompliancewiththe  
latestrevisionofMIL-STD-883,ClassB,makingitideallysuitedtomilitary  
temperatureapplicationsdemandingthehighestlevelofperformanceand  
reliability.  
FunctionalBlockDiagram  
A0  
VCC  
GND  
262,144 BIT  
MEMORY ARRAY  
ADDRESS  
DECODER  
A14  
I/O0  
I/O CONTROL  
INPUT  
DATA  
CIRCUIT  
I/O7  
,
CS  
OE  
CONTROL  
CIRCUIT  
2946 drw 01  
WE  
FEBRUARY 2001  
1
©2000IntegratedDeviceTechnology,Inc.  
DSC-2946/9  

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