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IDT70V9359L7BFGI PDF预览

IDT70V9359L7BFGI

更新时间: 2024-11-27 13:08:39
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
16页 306K
描述
Dual-Port SRAM, 8KX18, 18ns, CMOS, PBGA100, FPBGA-100

IDT70V9359L7BFGI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:BGA
包装说明:FPBGA-100针数:100
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.83
最长访问时间:18 ns其他特性:FLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 代码:S-PBGA-B100JESD-609代码:e3
长度:10 mm内存密度:147456 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:18
功能数量:1端子数量:100
字数:8192 words字数代码:8000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:8KX18
封装主体材料:PLASTIC/EPOXY封装代码:LFBGA
封装形状:SQUARE封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.5 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:10 mm
Base Number Matches:1

IDT70V9359L7BFGI 数据手册

 浏览型号IDT70V9359L7BFGI的Datasheet PDF文件第2页浏览型号IDT70V9359L7BFGI的Datasheet PDF文件第3页浏览型号IDT70V9359L7BFGI的Datasheet PDF文件第4页浏览型号IDT70V9359L7BFGI的Datasheet PDF文件第5页浏览型号IDT70V9359L7BFGI的Datasheet PDF文件第6页浏览型号IDT70V9359L7BFGI的Datasheet PDF文件第7页 
IDT70V9359/49L  
HIGH-SPEED 3.3V 8/4K x 18  
SYNCHRONOUS PIPELINED  
DUAL-PORT STATIC RAM  
Features:  
Full synchronous operation on both ports  
– 3.5ns setup to clock and 0ns hold on all control, data, and  
addressinputs  
– Data input, address, and control registers  
– Fast 6.5ns clock to data out in the Pipelined output mode  
– Self-timedwriteallowsfastcycletime  
– 10ns cycle time, 100MHz operation in Pipelined output mode  
Separate upper-byte and lower-byte controls for  
multiplexed bus and bus matching compatibility  
LVTTL- compatible, single 3.3V (±0.3V) power supply  
Industrial temperature range (–40°C to +85°C) is  
available for 83 MHz  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed clock to data access  
– Commercial:6.5/7.5/9ns(max.)  
– Industrial: 7.5ns (max.)  
Low-power operation  
– IDT70V9359/49L  
Active:450mW(typ.)  
Standby: 1.5mW (typ.)  
Flow-Through or Pipelined output mode on either port via  
the FT/PIPE pins  
Counter enable and reset features  
Dual chip enables allow for depth expansion without  
additional logic  
Available in a 100-pin Thin Quad Flatpack (TQFP) and 100-  
pin Fine Pitch Ball Grid Array (fpBGA) packages.  
FunctionalBlockDiagram  
R/  
W
L
L
R/  
W
R
R
UB  
UB  
CE0L  
CE1L  
CE0R  
CE1R  
1
0
1
0
0/1  
0/1  
LB  
OE  
L
L
LB  
OE  
R
R
1b 0b  
0a 1a  
1a 0a  
0b 1b  
b
FT/PIPE  
L
0/1  
0/1  
b
a
a
FT/PIPE  
R
I/O9L-I/O17L  
I/O0L-I/O8L  
I/O9R-I/O17R  
I/O0R-I/O8R  
(1)  
I/O  
Control  
I/O  
Control  
(1)  
A12L  
A12R  
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
MEMORY  
ARRAY  
A
0R  
CLK  
A
0L  
L
L
R
R
CLK  
ADS  
CNTEN  
CNTRST  
ADS  
CNTEN  
R
L
L
CNTRST  
R
5638 drw 01  
NOTE:  
1. A12 is a NC for IDT70V9349.  
AUGUST 2003  
1
©2003IntegratedDeviceTechnology,Inc.  
DSC-5638/3  

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