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IDT70V9189L7PFGI PDF预览

IDT70V9189L7PFGI

更新时间: 2024-09-17 19:34:35
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器输出元件内存集成电路
页数 文件大小 规格书
15页 209K
描述
Dual-Port SRAM, 64KX9, 7.5ns, CMOS, PQFP100, TQFP-100

IDT70V9189L7PFGI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:TQFP-100针数:100
Reach Compliance Code:compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.84
最长访问时间:7.5 ns其他特性:PIPELINED OUTPUT MODE; SELF-TIMED WRITE CYCLE
JESD-30 代码:S-PQFP-G100JESD-609代码:e3
长度:14 mm内存密度:589824 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:9
湿度敏感等级:3功能数量:1
端子数量:100字数:65536 words
字数代码:64000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:64KX9封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:14 mmBase Number Matches:1

IDT70V9189L7PFGI 数据手册

 浏览型号IDT70V9189L7PFGI的Datasheet PDF文件第2页浏览型号IDT70V9189L7PFGI的Datasheet PDF文件第3页浏览型号IDT70V9189L7PFGI的Datasheet PDF文件第4页浏览型号IDT70V9189L7PFGI的Datasheet PDF文件第5页浏览型号IDT70V9189L7PFGI的Datasheet PDF文件第6页浏览型号IDT70V9189L7PFGI的Datasheet PDF文件第7页 
PRELIMINARY  
IDT70V9189L  
HIGH-SPEED 3.3V 64K x 9  
SYNCHRONOUS PIPELINED  
DUAL-PORT STATIC RAM  
Features:  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed clock to data access  
– Commercial: 7.5/9/12ns (max.)  
Low-power operation  
Full synchronous operation on both ports  
– 4ns setup to clock and 0ns hold on all control, data, and  
addressinputs  
– Data input, address, and control registers  
– Fast 7.5ns clock to data out in the Pipelined output mode  
– Self-timedwriteallowsfastcycletime  
– IDT70V9189L  
Active: 500mW (typ.)  
Standby: 1.5mW (typ.)  
– 12ns cycle time, 83MHz operation in Pipelined output mode  
LVTTL- compatible, single 3.3V (±0.3V) power supply  
Industrial temperature range (–40°C to +85°C) is  
available for selected speeds  
Flow-Through or Pipelined output mode on either port via  
the FT/PIPE pins  
Counter enable and reset features  
Dual chip enables allow for depth expansion without  
additional logic  
Available in a 100-pin Thin Quad Flatpack (TQFP)  
FunctionalBlockDiagram  
R/WR  
OER  
R/WL  
OEL  
CE0L  
CE1L  
CE0R  
CE1R  
1
1
0
0
0/1  
0/1  
1
0
1
0
0/1  
0/1  
FT/PIPEL  
FT/PIPER  
I/O0L - I/O8L  
I/O0R - I/O8R  
I/O  
Control  
I/O  
Control  
A15L  
A15R  
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
MEMORY  
ARRAY  
A0R  
A0L  
CLKR  
CLKL  
ADSR  
ADSL  
CNTENL  
CNTRSTL  
CNTENR  
CNTRSTR  
4860 drw 01  
AUGUST 1999  
1
©1999IntegratedDeviceTechnology,Inc.  
DSC-4860/1  

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