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IDT70V631S12BCGI PDF预览

IDT70V631S12BCGI

更新时间: 2024-10-28 13:08:39
品牌 Logo 应用领域
艾迪悌 - IDT 存储内存集成电路静态存储器
页数 文件大小 规格书
23页 306K
描述
Dual-Port SRAM, 256KX18, 12ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, BGA-256

IDT70V631S12BCGI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:BGA
包装说明:LBGA,针数:256
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.31
最长访问时间:12 nsJESD-30 代码:S-PBGA-B256
JESD-609代码:e1长度:17 mm
内存密度:4718592 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:18湿度敏感等级:3
功能数量:1端子数量:256
字数:262144 words字数代码:256000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:256KX18
封装主体材料:PLASTIC/EPOXY封装代码:LBGA
封装形状:SQUARE封装形式:GRID ARRAY, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.7 mm
最大供电电压 (Vsup):3.45 V最小供电电压 (Vsup):3.15 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:17 mm
Base Number Matches:1

IDT70V631S12BCGI 数据手册

 浏览型号IDT70V631S12BCGI的Datasheet PDF文件第2页浏览型号IDT70V631S12BCGI的Datasheet PDF文件第3页浏览型号IDT70V631S12BCGI的Datasheet PDF文件第4页浏览型号IDT70V631S12BCGI的Datasheet PDF文件第5页浏览型号IDT70V631S12BCGI的Datasheet PDF文件第6页浏览型号IDT70V631S12BCGI的Datasheet PDF文件第7页 
HIGH-SPEED 3.3V 256K x 18  
ASYNCHRONOUS DUAL-PORT  
STATIC RAM  
IDT70V631S  
Features  
True Dual-Port memory cells which allow simultaneous  
access of the same memory location  
High-speed access  
Fully asynchronous operation from either port  
Separate byte controls for multiplexed bus and bus  
matching compatibility  
Supports JTAG features compliant to IEEE 1149.1  
– Due to limited pin count, JTAG is not supported on the  
128-pin TQFP package.  
– Commercial:10/12/15ns(max.)  
– Industrial: 12ns (max.)  
Dual chip enables allow for depth expansion without  
external logic  
IDT70V631 easily expands data bus width to 36 bits or  
more using the Master/Slave select when cascading more  
than one device  
M/S = VIH for BUSY output flag on Master,  
M/S = VIL for BUSY input on Slave  
Busy and Interrupt Flags  
LVTTL-compatible, single 3.3V (±150mV) power supply for  
core  
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)  
power supply for I/Os and control signals on each port  
Available in a 128-pin Thin Quad Flatpack, 208-ball fine  
pitch Ball Grid Array, and 256-ball Ball Grid Array  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
Functional Block Diagram  
UBL  
UB  
R
LBL  
LB  
R
R/  
WL  
R/WR  
B
E
0
L
B
E
1
L
B
E
1
B
E
0
CE0L  
CE0R  
R
R
CE1L  
CE1R  
OEL  
OER  
Dout0-8_L  
Dout0-8_R  
Dout9-17_L  
Dout9-17_R  
256K x 18  
MEMORY  
ARRAY  
Din_L  
I/O0L- I/O17L  
Din_R  
I/O0R - I/O17R  
A
17R  
0R  
Address  
Decoder  
Address  
Decoder  
A
17L  
0L  
ADDR_L  
ADDR_R  
A
A
OE  
L
OER  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE0R  
CE1R  
CE0L  
CE1L  
R/WL  
R/WR  
BUSY  
R
BUSY  
SEM  
INT  
L
L
M/S  
SEM  
INT  
R
L
R
TMS  
TCK  
TDI  
JTAG  
TDO  
TRST  
5622 drw 01  
NOTES:  
1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).  
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).  
OCTOBER 2003  
1
DSC-5622/5  
©2003IntegratedDeviceTechnology,Inc.  

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