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IDT70V3579S5DR8 PDF预览

IDT70V3579S5DR8

更新时间: 2024-11-27 05:03:15
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器输出元件内存集成电路
页数 文件大小 规格书
17页 190K
描述
Dual-Port SRAM, 32KX36, 5ns, PQFP208, PLASTIC, QFP-208

IDT70V3579S5DR8 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:FQFP,针数:208
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.3
最长访问时间:5 ns其他特性:PIPELINED OUTPUT MODE, SELF-TIMED WRITE CYCLE
JESD-30 代码:S-PQFP-G208JESD-609代码:e0
长度:28 mm内存密度:1179648 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:36
湿度敏感等级:3功能数量:1
端子数量:208字数:32768 words
字数代码:32000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:32KX36封装主体材料:PLASTIC/EPOXY
封装代码:FQFP封装形状:SQUARE
封装形式:FLATPACK, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):225认证状态:Not Qualified
座面最大高度:4.1 mm最大供电电压 (Vsup):3.45 V
最小供电电压 (Vsup):3.15 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:28 mmBase Number Matches:1

IDT70V3579S5DR8 数据手册

 浏览型号IDT70V3579S5DR8的Datasheet PDF文件第2页浏览型号IDT70V3579S5DR8的Datasheet PDF文件第3页浏览型号IDT70V3579S5DR8的Datasheet PDF文件第4页浏览型号IDT70V3579S5DR8的Datasheet PDF文件第5页浏览型号IDT70V3579S5DR8的Datasheet PDF文件第6页浏览型号IDT70V3579S5DR8的Datasheet PDF文件第7页 
HIGH-SPEED 3.3V 32K x 36  
SYNCHRONOUS PIPELINED  
DUAL-PORT STATIC RAM  
WITH 3.3V OR 2.5V INTERFACE  
IDT70V3579S  
Features:  
address inputs @ 133MHz  
Data input, address, byte enable and control registers  
– Self-timedwriteallowsfastcycletime  
Separate byte controls for multiplexed bus and bus  
matching compatibility  
LVTTL- compatible, single 3.3V (±150mV) power supply for  
core  
LVTTL compatible, selectable 3.3V (±150mV)/2.5V (±125mV)  
power supply for I/Os and control signals on each port  
Industrial temperature range (-40°C to +85°C) is  
available for selected speeds  
Available in a 208-pin Plastic Quad Flatpack (PQFP) and  
208-pin fine pitch Ball Grid Array, and 256-pin Ball Grid  
Array  
True Dual-Port memory cells which allow simultaneous  
access of the same memory location  
High-speed clock to data access  
– Commercial:4.2/5/6ns (max.)  
Industrial:5ns (max)  
Pipelined output mode  
Counter enable and reset features  
Dual chip enables allow for depth expansion without  
additional logic  
Full synchronous operation on both ports  
– 7.5ns cycle time, 133MHzoperation(9.6Gbps bandwidth)  
– Fast 4.2ns clock to data out  
– 1.8ns setup to clock and 0.7ns hold on all control, data, and  
Functional Block Diagram  
BE3L  
BE3R  
BE2R  
BE1R  
BE0R  
BE2L  
BE1L  
BE0L  
R/W  
L
R/WR  
B
B
B
B
B
B B B  
W W W W W WW W  
0
L
1
L
2
L
3
L
3
R
2
1
0
R
CE0L  
R R  
CE0R  
CE1L  
CE1R  
OE  
L
OER  
Dout0-8_L  
Dout0-8_R  
Dout9-17_R  
Dout18-26_R  
Dout9-17_L  
Dout18-26_L  
Dout27-35_L  
Dout27-35_R  
32K x 36  
MEMORY  
ARRAY  
I/O0L- I/O35L  
Din_L  
I/O0R - I/O35R  
Din_R  
,
CLK  
L
CLKR  
A
14L  
A
A
14R  
0R  
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
A
0L  
L
ADDR_L  
ADDR_R  
CNTRST  
ADS  
CNTEN  
CNTRST  
ADS  
CNTEN  
R
R
L
L
R
4830 tbl 01  
DECEMBER 2001  
1
DSC 4830/14  
©2001IntegratedDeviceTechnology,Inc.  

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