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IDT70V3569S4BFGI PDF预览

IDT70V3569S4BFGI

更新时间: 2024-11-23 13:08:39
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
16页 188K
描述
Dual-Port SRAM, 16KX36, 4.2ns, PBGA208, FINE PITCH, BGA-208

IDT70V3569S4BFGI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:BGA
包装说明:TFBGA,针数:208
Reach Compliance Code:compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.43
最长访问时间:4.2 ns其他特性:PIPELINED OUTPUT MODE; SELF TIMED WRITE CYCLE
JESD-30 代码:S-PBGA-B208JESD-609代码:e1
长度:15 mm内存密度:589824 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:36
湿度敏感等级:3功能数量:1
端子数量:208字数:16384 words
字数代码:16000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:16KX36封装主体材料:PLASTIC/EPOXY
封装代码:TFBGA封装形状:SQUARE
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):3.45 V
最小供电电压 (Vsup):3.15 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN SILVER COPPER
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
宽度:15 mmBase Number Matches:1

IDT70V3569S4BFGI 数据手册

 浏览型号IDT70V3569S4BFGI的Datasheet PDF文件第2页浏览型号IDT70V3569S4BFGI的Datasheet PDF文件第3页浏览型号IDT70V3569S4BFGI的Datasheet PDF文件第4页浏览型号IDT70V3569S4BFGI的Datasheet PDF文件第5页浏览型号IDT70V3569S4BFGI的Datasheet PDF文件第6页浏览型号IDT70V3569S4BFGI的Datasheet PDF文件第7页 
HIGH-SPEED 3.3V 16K x 36  
SYNCHRONOUS PIPELINED  
DUAL-PORT STATIC RAM  
WITH 3.3V OR 2.5V INTERFACE  
IDT70V3569S  
Features:  
address inputs @ 133MHz  
Data input, address, byte enable and control registers  
– Self-timedwriteallowsfastcycletime  
Separate byte controls for multiplexed bus and bus  
matching compatibility  
LVTTL- compatible, single 3.3V (±150mV) power supply for  
core  
LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV)  
power supply for I/Os and control signals on each port  
Industrial temperature range (-40°C to +85°C) is  
available for selected speeds  
Available in a 208-pin Plastic Quad Flatpack (PQFP),  
208-ball fine-pitch Ball Grid Array, and 256-pin Ball  
GridArray  
True Dual-Port memory cells which allow simultaneous  
access of the same memory location  
High-speed clock to data access  
– Commercial:4.2/5/6ns (max.)  
Industrial:5/6ns (max)  
Pipelined output mode  
Counter enable and reset features  
Dual chip enables allow for depth expansion without  
additional logic  
Full synchronous operation on both ports  
– 7.5ns cycle time, 133MHzoperation(9.6Gbps bandwidth)  
– Fast 4.2ns clock to data out  
– 1.8ns setup to clock and 0.7ns hold on all control, data, and  
FunctionalBlockDiagram  
BE3L  
BE3R  
2R  
BE  
BE2L  
BE1L  
BE1R  
BE0R  
BE0L  
L
W
R/  
WR  
R/  
B
B
B
B
B
B B B  
W W W W W WW W  
0
L
1
L
2
L
3
L
3
R
2
1
0
R
CE0L  
R R  
CE0R  
1R  
1L  
CE  
CE  
OEL  
OER  
Dout0-8_L  
Dout0-8_R  
Dout9-17_R  
Dout18-26_R  
Dout9-17_L  
Dout18-26_L  
Dout27-35_L  
Dout27-35_R  
16K x 36  
MEMORY  
ARRAY  
0L  
35L  
I/O - I/O  
Din_L  
0R  
35R  
I/O - I/O  
Din_R  
,
L
CLK  
R
CLK  
13L  
A
13R  
0R  
A
A
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
0L  
A
ADDR_L  
ADDR_R  
CNTRSTL  
CNTRSTR  
R
ADS  
ADSL  
L
R
CNTEN  
CNTEN  
4831 tbl 01  
APRIL 2001  
1
DSC 4831/8  
©2001IntegratedDeviceTechnology,Inc.  

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