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IDT70V05S55PFG8 PDF预览

IDT70V05S55PFG8

更新时间: 2024-11-08 10:24:11
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
22页 180K
描述
Dual-Port SRAM, 8KX8, 55ns, CMOS, PQFP64, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100

IDT70V05S55PFG8 数据手册

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IDT70V05S/L  
HIGH-SPEED 3.3V  
8K x 8 DUAL-PORT  
STATIC RAM  
Features  
using the Master/Slave select when cascading more than  
one device  
M/S = VIH for BUSY output flag on Master  
M/S = VIL for BUSY input on Slave  
Interrupt Flag  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
TTL-compatible, single 3.3V (±0.3V) power supply  
Available in 68-pin PGA and PLCC, and a 64-pin TQFP  
Industrial temperature range (-40°C to +85°C) is available  
for selected speeds  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
Commercial: 15/20/25/35/55ns (max.)  
Industrial:20ns (max.)  
Low-power operation  
IDT70V05S  
Active:400mW(typ.)  
Standby: 3.3mW (typ.)  
IDT70V05L  
Active:380mW(typ.)  
Standby: 660µW (typ.)  
IDT70V05 easily expands data bus width to 16 bits or more  
Functional Block Diagram  
OEL  
OER  
CE  
L
CE  
R/W  
R
R/W  
L
R
,
I/O0L- I/O7L  
I/O0R-I/O7R  
I/O  
Control  
I/O  
Control  
(1,2)  
L
(1,2)  
R
BUSY  
BUSY  
A
12L  
A
12R  
0R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
0L  
A
13  
13  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE  
OE  
L
L
CE  
OE  
R/W  
R
R
R
R/W  
L
SEM  
L
SEM  
R
M/S  
(2)  
(2)  
INTL  
INTR  
2942 drw 01  
NOTES:  
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
2. BUSY outputs and INT outputs are non-tri-stated push-pull.  
DECEMBER 2001  
1
DSC 2941/7  
©2001IntegratedDeviceTechnology,Inc.  

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