Datasheet > IDT70T3599S-133DR

IDT70T3599S-133DR

更新时间： 2024-11-27 23:14:07

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
28页	431K
描述
HIGH-SPEED 2.5V 256/128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE

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HIGH-SPEED 2.5V

256/128/64K x 36

IDT70T3519/99/89S

SYNCHRONOUS

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

Features:

– Data input, address, byte enable and control registers

– Self-timedwriteallowsfastcycletime

Separate byte controls for multiplexed bus and bus

matching compatibility

Dual Cycle Deselect (DCD) for Pipelined Output Mode

2.5V (±100mV) power supply for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

Industrial temperature range (-40°C to +85°C) is

available at 166MHz and 133MHz

Available in a 256-pin Ball Grid Array (BGA), a 208-pin

Plastic Quad Flatpack (PQFP) and 208-pin fine pitch Ball

Grid Array (fpBGA)

Supports JTAG features compliant with IEEE 1149.1

Due to limited pin count JTAG is not supported on the 208-

pin PQFP package

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed data access

◆

– Commercial: 3.4 (200MHz)/3.6ns (166MHz)/

4.2ns (133MHz)(max.)

◆

– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

Counter enable and repeat features

Dual chip enables allow for depth expansion without

additional logic

Interrupt and Collision Detection Flags

Full synchronous operation on both ports

– 5ns cycle time, 200MHz operation (14Gbps bandwidth)

– Fast 3.4ns clock to data out

◆

– 1.5ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 200MHz

FunctionalBlockDiagram

BE3R

BE3L

BE2L

BE1L

BE0L

BE2R

BE1R

BE0R

FT/PIPE

0a 1a

0b 1b

0c 1c

0d 1d

1d 0d

1c 0c

1b 0b

1a 0a

FT/PIPER

1/0

R/WL

R/WR

CE0L

CE0R

CE1R

CE1L

B B B

1/0

W W W W W W W W

Dout0-8_L

Dout0-8_R

Dout9-17_L

Dout18-26_L

Dout27-35_L

Dout9-17_R

Dout18-26_R

Dout27-35_R

1d 0d 1c 0c

1b 0b 1a 0a

0a 1a 0b 1b

0c 1c 0d 1d

d c b a

0/1

FT/PIPE

a bc d

256/128/64K x 36

MEMORY

ARRAY

I/O0L - I/O35L

I/O0R - I/O35R

Din_L

Din_R

CLK

(1)

17R

(1)

17L

Counter/

Address

Reg.

Counter/

Address

Reg.

REPEAT

ADS

REPEAT

ADS

CNTEN

ADDR_R

ADDR_L

CNTEN

TDI

TCK

TMS

TRST

INTERRUPT

CE0

CE1

JTAG

COLLISION

DETECTION

LOGIC

CE1

TDO

R/W

COL

INT

(2)

ZZR

CONTROL

LOGIC

5666 drw 01

NOTES:

1. Address A17 is a NC for the IDT70T3599. Also, Addresses A17 and A16 are NC's for the IDT70T3589.

2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx

APRIL 2004

and the sleep mode pins themselves (ZZx) are not affected during sleep mode.

DSC 5666/6

12 3 4 5 6 7...28

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与IDT70T3599S-133DR相关器件

型号	品牌	获取价格	描述	数据表
IDT70T3599S133DRG	IDT	获取价格	Dual-Port SRAM, 128KX36, 15ns, CMOS, PQFP208, 28 X 28 MM, 3.50 MM HEIGHT, PLASTIC, GREEN,
IDT70T3599S133DRI	IDT	获取价格	HIGH-SPEED 2.5V 256/128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERF
IDT70T3599S-133DRI	IDT	获取价格	HIGH-SPEED 2.5V 256/128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERF
IDT70T3599S166BC	IDT	获取价格	HIGH-SPEED 2.5V 256/128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERF
IDT70T3599S-166BC	IDT	获取价格	HIGH-SPEED 2.5V 256/128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERF
IDT70T3599S166BC8	IDT	获取价格	Dual-Port SRAM, 128KX36, 12ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, BGA-
IDT70T3599S166BCG	IDT	获取价格	Dual-Port SRAM, 128KX36, 12ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, GREE
IDT70T3599S166BCGI8	IDT	获取价格	Multi-Port SRAM, 128KX36, 12ns, CMOS, PBGA256
IDT70T3599S166BCI	IDT	获取价格	HIGH-SPEED 2.5V 256/128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERF
IDT70T3599S-166BCI	IDT	获取价格	HIGH-SPEED 2.5V 256/128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERF

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