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IDT70T3519S-200DRI PDF预览

IDT70T3519S-200DRI

更新时间： 2024-10-29 05:12:11
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
28页 431K
描述
HIGH-SPEED 2.5V 256/128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE

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IDT70T3519S-200DRI 数据手册

 浏览型号IDT70T3519S-200DRI的Datasheet PDF文件第2页浏览型号IDT70T3519S-200DRI的Datasheet PDF文件第3页浏览型号IDT70T3519S-200DRI的Datasheet PDF文件第4页浏览型号IDT70T3519S-200DRI的Datasheet PDF文件第5页浏览型号IDT70T3519S-200DRI的Datasheet PDF文件第6页浏览型号IDT70T3519S-200DRI的Datasheet PDF文件第7页 
HIGH-SPEED 2.5V  
256/128/64K x 36  
IDT70T3519/99/89S  
SYNCHRONOUS  
DUAL-PORT STATIC RAM  
WITH 3.3V OR 2.5V INTERFACE  
Features:  
– Data input, address, byte enable and control registers  
– Self-timedwriteallowsfastcycletime  
Separate byte controls for multiplexed bus and bus  
matching compatibility  
Dual Cycle Deselect (DCD) for Pipelined Output Mode  
2.5V (±100mV) power supply for core  
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V  
(±100mV) power supply for I/Os and control signals on  
each port  
Industrial temperature range (-40°C to +85°C) is  
available at 166MHz and 133MHz  
Available in a 256-pin Ball Grid Array (BGA), a 208-pin  
Plastic Quad Flatpack (PQFP) and 208-pin fine pitch Ball  
Grid Array (fpBGA)  
Supports JTAG features compliant with IEEE 1149.1  
Due to limited pin count JTAG is not supported on the 208-  
pin PQFP package  
◆
True Dual-Port memory cells which allow simultaneous  
access of the same memory location  
High-speed data access  
◆
◆
– Commercial: 3.4 (200MHz)/3.6ns (166MHz)/  
4.2ns (133MHz)(max.)  
◆
◆
◆
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)  
Selectable Pipelined or Flow-Through output mode  
Counter enable and repeat features  
Dual chip enables allow for depth expansion without  
additional logic  
Interrupt and Collision Detection Flags  
Full synchronous operation on both ports  
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)  
– Fast 3.4ns clock to data out  
◆
◆
◆
◆
◆
◆
◆
◆
◆
– 1.5ns setup to clock and 0.5ns hold on all control, data, and  
address inputs @ 200MHz  
FunctionalBlockDiagram  
BE3R  
BE3L  
BE2L  
BE1L  
BE0L  
BE2R  
BE1R  
BE0R  
FT/PIPE  
L
0a 1a  
a
0b 1b  
b
0c 1c  
c
0d 1d  
d
1d 0d  
d
1c 0c  
c
1b 0b  
b
1a 0a  
a
FT/PIPER  
1/0  
1/0  
R/WL  
R/WR  
CE0L  
CE0R  
1
1
CE1R  
CE1L  
0
0
B
B B B  
B
B B B  
1/0  
1/0  
W W W W W W W W  
0
L
1
L
2
L
3
L
3
R
2
1
R
0
R
R
OE  
R
OE  
L
Dout0-8_L  
Dout0-8_R  
Dout9-17_L  
Dout18-26_L  
Dout27-35_L  
Dout9-17_R  
Dout18-26_R  
Dout27-35_R  
,
1d 0d 1c 0c  
1b 0b 1a 0a  
0a 1a 0b 1b  
0c 1c 0d 1d  
d c b a  
0/1  
0/1  
FT/PIPE  
R
FT/PIPE  
L
a bc d  
256/128/64K x 36  
MEMORY  
ARRAY  
I/O0L - I/O35L  
I/O0R - I/O35R  
Din_L  
Din_R  
,
CLK  
R
CLK  
L
(1)  
17R  
(1)  
17L  
A
A
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
A
0L  
REPEAT  
ADS  
A
0R  
REPEAT  
ADS  
CNTEN  
ADDR_R  
ADDR_L  
L
R
R
L
R
CNTEN  
L
TDI  
TCK  
TMS  
TRST  
INTERRUPT  
CE0  
CE1  
R
CE  
0
L
JTAG  
COLLISION  
DETECTION  
LOGIC  
R
CE1  
TDO  
L
R/  
W
L
R/W  
R
COL  
L
COL  
R
INT  
L
INT  
R
(2)  
(2)  
ZZR  
ZZ  
CONTROL  
LOGIC  
ZZ  
L
5666 drw 01  
NOTES:  
1. Address A17 is a NC for the IDT70T3599. Also, Addresses A17 and A16 are NC's for the IDT70T3589.  
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx  
APRIL 2004  
and the sleep mode pins themselves (ZZx) are not affected during sleep mode.  
1
DSC 5666/6  
©2004IntegratedDeviceTechnology,Inc.  
1234567...28

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