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IDT7034L15PF PDF预览

IDT7034L15PF

更新时间: 2024-11-27 22:13:27
品牌 Logo 应用领域
艾迪悌 - IDT 存储内存集成电路静态存储器
页数 文件大小 规格书
19页 201K
描述
HIGH-SPEED 4K x 18 DUAL-PORT STATIC RAM

IDT7034L15PF 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:14 X 14 MM, 1.40 MM HEIGHT, TQFP-100针数:100
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.45
Is Samacsys:N最长访问时间:15 ns
I/O 类型:COMMONJESD-30 代码:S-PQFP-G100
JESD-609代码:e0长度:14 mm
内存密度:73728 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:18湿度敏感等级:3
功能数量:1端口数量:2
端子数量:100字数:4096 words
字数代码:4000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:4KX18输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP100,.63SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:5 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.0015 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.26 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:14 mm
Base Number Matches:1

IDT7034L15PF 数据手册

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IDT7034S/L  
HIGH-SPEED  
4K x 18 DUAL-PORT  
STATIC RAM  
Features:  
using the Master/Slave select when cascading more than  
one device  
M/S = H for BUSY output flag on Master  
M/S = L for BUSY input on Slave  
Interrupt Flag  
On-chip port arbitration logic  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
— Commercial: 15/20ns (max.)  
Low-power operation  
— IDT7034S  
Full on-chip hardware support of semaphore signaling  
between ports  
Active: 850mW (typ.)  
Standby: 5mW (typ.)  
— IDT7034L  
Fully asynchronous operation from either port  
Battery backup operation—2V data retention  
TTL-compatible, single 5V (±10%) power supply  
Available in 100-pin Thin Quad Flatpack  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Active: 850mW (typ.)  
Standby: 1mW (typ.)  
Separate upper-byte and lower-byte control for multiplexed  
bus compatibility  
IDT7034 easily expands data bus width to 36 bits or more  
Functional Block Diagram  
R/WL  
UBL  
R/WR  
UBR  
LBL  
CEL  
OEL  
LBR  
CER  
OER  
I/O9L-I/O17L  
I/O9R-I/O17R  
.
I/O  
I/O  
Control  
Control  
I/O0L-I/O8L  
0R  
I/O -I/O  
8R  
(1,2)  
BUSYL  
(1,2)  
BUSYR  
A11L  
A11R  
A0R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A0L  
13  
13  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CER  
OER  
CEL  
OEL  
R/WL  
R/WR  
SEMR  
(2)  
SEML  
(2)  
INTR  
M/S  
INTL  
4089 drw 01  
NOTES:  
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
2. BUSY outputs and INT outputs are non-tri-stated push-pull.  
SEPTEMBER 1999  
1
DSC 4089/6  
©1999IntegratedDeviceTechnology,Inc.  

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