Datasheet > IDT7027S

IDT7027S

更新时间： 2024-10-26 23:01:07

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
19页	161K
描述
HIGH-SPEED 32K x 16 DUAL-PORT STATIC RAM

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中文翻译

获取价格

数据手册

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IDT7027S 数据手册

HIGH-SPEED

IDT7027S/L

32K x 16 DUAL-PORT

STATIC RAM

Features

◆

external logic

True Dual-Ported memory cells which allow simultaneous

◆

IDT7027 easily expands data bus width to 32 bits or more

using the Master/Slave select when cascading more than

one device

M/S = VIH for BUSY output flag on Master,

M/S = VIL for BUSY input on Slave

access of the same memory location

High-speed access

◆

–

Military: 25/35/55ns (max)

– Industrial: 25ns (max.)

– Commercial:20/25/35/55ns (max.)

Low-power operation

◆

Busy and Interrupt Flags

On-chip port arbitration logic

– IDT7027S

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

TTL-compatible, single 5V (±10%) power supply

Available in 100-pin Thin Quad Flatpack (TQFP) and 108-pin

Ceramic PinGridArray(PGA)

Active: 750mW (typ.)

Standby: 5mW (typ.)

– IDT7027L

◆

Active: 750mW (typ.)

Standby: 1mW (typ.)

Separate upper-byte and lower-byte control for bus

matching capability.

◆

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Dual chip enables allow for depth expansion without

FunctionalBlockDiagram

R/WL

UBL

UBR

CE0L

CE0R

CE1L

CE1R

OER

LBR

OEL

LBL

I/O^8-15L

I/O_8-15R

I/O

Control

I/O

Control

0-7L

I/O

I/O0-7R

(1,2)

BUSYR

BUSY_L

32Kx16

A14R

A0R

A14L

Address

Decoder

Address

Decoder

MEMORY

ARRAY

7027

A0L

A14L

A14R

A0R

CE0R

A0L

CE0L

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE1L

OEL

CE1R

OER

R/WR

SEML

INTL

SEMR

(2)

INTR

M/S⁽²⁾

3199 drw 01

NOTES:

1. BUSY is an input as a Slave (M/S=V^IL) and an output as a Master (M/S=VIH).

2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).

MAY 2000

DSC 3199/7

12 3 4 5 6 7...19

中文翻译

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