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IDT7027L55GG PDF预览

IDT7027L55GG

更新时间: 2024-10-27 12:58:03
品牌 Logo 应用领域
艾迪悌 - IDT 存储内存集成电路静态存储器
页数 文件大小 规格书
19页 161K
描述
Dual-Port SRAM, 32KX16, 55ns, CMOS, CPGA108, CERAMIC, PGA-108

IDT7027L55GG 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:PGA
包装说明:PGA,针数:108
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.42
Is Samacsys:N最长访问时间:55 ns
其他特性:INTERRUPT FLAG; SEMAPHORE; AUTOMATIC POWER-DOWN; LOW POWER STANDBY MODEJESD-30 代码:S-CPGA-P108
JESD-609代码:e3长度:30.48 mm
内存密度:524288 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:16功能数量:1
端口数量:2端子数量:108
字数:32768 words字数代码:32000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:32KX16
输出特性:3-STATE可输出:YES
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:PGA
封装形状:SQUARE封装形式:GRID ARRAY
并行/串行:PARALLEL峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:5.207 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:PIN/PEG
端子节距:2.54 mm端子位置:PERPENDICULAR
处于峰值回流温度下的最长时间:30宽度:30.48 mm
Base Number Matches:1

IDT7027L55GG 数据手册

 浏览型号IDT7027L55GG的Datasheet PDF文件第2页浏览型号IDT7027L55GG的Datasheet PDF文件第3页浏览型号IDT7027L55GG的Datasheet PDF文件第4页浏览型号IDT7027L55GG的Datasheet PDF文件第5页浏览型号IDT7027L55GG的Datasheet PDF文件第6页浏览型号IDT7027L55GG的Datasheet PDF文件第7页 
HIGH-SPEED  
IDT7027S/L  
32K x 16 DUAL-PORT  
STATIC RAM  
Features  
external logic  
True Dual-Ported memory cells which allow simultaneous  
IDT7027 easily expands data bus width to 32 bits or more  
using the Master/Slave select when cascading more than  
one device  
M/S = VIH for BUSY output flag on Master,  
M/S = VIL for BUSY input on Slave  
access of the same memory location  
High-speed access  
Military: 25/35/55ns (max)  
Industrial: 25ns (max.)  
– Commercial:20/25/35/55ns (max.)  
Low-power operation  
Busy and Interrupt Flags  
On-chip port arbitration logic  
IDT7027S  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
TTL-compatible, single 5V (±10%) power supply  
Available in 100-pin Thin Quad Flatpack (TQFP) and 108-pin  
Ceramic PinGridArray(PGA)  
Active: 750mW (typ.)  
Standby: 5mW (typ.)  
IDT7027L  
Active: 750mW (typ.)  
Standby: 1mW (typ.)  
Separate upper-byte and lower-byte control for bus  
matching capability.  
Industrial temperature range (40°C to +85°C) is available  
for selected speeds  
Dual chip enables allow for depth expansion without  
FunctionalBlockDiagram  
R/WL  
UBL  
WR  
R/  
UBR  
CE0L  
CE0R  
CE1L  
CE1R  
OER  
LBR  
OEL  
LBL  
I/O8-15L  
I/O8-15R  
I/O  
Control  
I/O  
Control  
0-7L  
I/O  
I/O0-7R  
(1,2)  
(1,2)  
BUSYR  
BUSYL  
.
32Kx16  
A14R  
A0R  
A14L  
Address  
Decoder  
Address  
Decoder  
MEMORY  
ARRAY  
7027  
A0L  
A14L  
A14R  
A0R  
CE0R  
A0L  
CE0L  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE1L  
OEL  
CE1R  
OER  
WL  
R/  
R/WR  
SEML  
INTL  
SEMR  
(2)  
(2)  
INTR  
M/S(2)  
3199 drw 01  
NOTES:  
1. BUSY is an input as a Slave (M/S=VIL) and an output as a Master (M/S=VIH).  
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).  
MAY 2000  
1
DSC 3199/7  
©2000IntegratedDeviceTechnology,Inc.  

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