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IDT7026L35GI PDF预览

IDT7026L35GI

更新时间: 2024-11-10 13:08:39
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
18页 239K
描述
Dual-Port SRAM, 16KX16, 35ns, CMOS, CPGA84, CERAMIC, PGA-84

IDT7026L35GI 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Active零件包装代码:PGA
包装说明:PGA, PGA84M,11X11针数:84
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.15
Is Samacsys:N最长访问时间:35 ns
其他特性:16K X 16 DUAL PORT SRAMI/O 类型:COMMON
JESD-30 代码:S-CPGA-P84JESD-609代码:e0
长度:27.94 mm内存密度:262144 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:16
功能数量:1端口数量:2
端子数量:84字数:16384 words
字数代码:16000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:16KX16输出特性:3-STATE
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:PGA
封装等效代码:PGA84M,11X11封装形状:SQUARE
封装形式:GRID ARRAY并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:5 V
认证状态:Not Qualified座面最大高度:5.207 mm
最大待机电流:0.01 A最小待机电流:4.5 V
子类别:SRAMs最大压摆率:0.295 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:PIN/PEG
端子节距:2.54 mm端子位置:PERPENDICULAR
处于峰值回流温度下的最长时间:30宽度:27.94 mm
Base Number Matches:1

IDT7026L35GI 数据手册

 浏览型号IDT7026L35GI的Datasheet PDF文件第2页浏览型号IDT7026L35GI的Datasheet PDF文件第3页浏览型号IDT7026L35GI的Datasheet PDF文件第4页浏览型号IDT7026L35GI的Datasheet PDF文件第5页浏览型号IDT7026L35GI的Datasheet PDF文件第6页浏览型号IDT7026L35GI的Datasheet PDF文件第7页 
HIGH-SPEED  
IDT7026S/L  
16K x 16 DUAL-PORT  
STATIC RAM  
Integrated Device Technology, Inc.  
FEATURES:  
• True Dual-Ported memory cells which allow simulta-  
neous access of the same memory location  
• High-speed access  
• IDT7026 easily expands data bus width to 32 bits or  
more using the Master/Slave select when cascading  
more than one device  
— Military: 25/35/55ns (max.)  
— Commercial: 20/25/35/55ns (max.)  
• Low-power operation  
• M/S = H for BUSY output flag on Master,  
M/S = L for BUSY input on Slave  
• On-chip port arbitration logic  
— IDT7026S  
• Full on-chip hardware support of semaphore signaling  
between ports  
Active: 750mW (typ.)  
Standby: 5mW (typ.)  
— IDT7026L  
Active: 750mW (typ.)  
Standby: 1mW (typ.)  
• Separate upper-byte and lower-byte control for  
multiplexed bus compatibility  
• Fully asynchronous operation from either port  
• TTL-compatible, single 5V (±10%) power supply  
• Available in 84-pin PGA and 84-pin PLCC  
• Industrial temperature range (–40°C to +85°C) is avail-  
able, tested to military electrical specifications  
FUNCTIONAL BLOCK DIAGRAM  
R/  
UB  
W
L
L
R/  
W
R
UB  
R
LB  
CE  
OE  
L
LB  
CE  
OER  
R
L
R
L
I/O8L-I/O15L  
I/O0L-I/O7L  
I/O8R-I/O15R  
I/O0R-I/O7R  
I/O  
Control  
I/O  
Control  
BUSY(1,2)  
L
BUSY (1,2)  
R
A
13L  
0L  
A
13R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
A
0R  
14  
14  
ARBITRATION  
SEMAPHORE  
LOGIC  
CEL  
CER  
SEM  
R
SEM  
L
M/S  
2939 drw 01  
NOTES:  
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
2. BUSY outputs are non-tri-stated push-pull.  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
OCTOBER 1996  
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.  
©1996 Integrated Device Technology, Inc.  
DSC 2939/3  
1
6.17  

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