Datasheet > 存储 > SRAM> IDT7007L15JB

IDT7007L15JB

更新时间： 2024-11-08 22:06:47

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
21页	257K
描述
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM

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中文翻译

获取价格

数据手册

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IDT7007L15JB 数据手册

HIGH-SPEED

IDT7007S/L

32K x 8 DUAL-PORT

STATIC RAM

Features

◆

using the Master/Slave select when cascading more than

one device

M/S = H for BUSY output flag on Master,

M/S = L for BUSY input on Slave

Interrupt Flag

On-chip port arbitration logic

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

◆

Military:25/35/55ns(max.)

Industrial: 55ns (max.)

◆

Commercial:15/20/25/35/55ns(max.)

Low-power operation

◆

Full on-chip hardware support of semaphore signaling

between ports

IDT7007S

◆

Fully asynchronous operation from either port

TTL-compatible, single 5V (±10%) power supply

Available in 68-pin PGA and PLCC and a 80-pin TQFP

Industrial temperature range (40°C to +85°C) is available

for selected speeds

Active:850mW(typ.)

Standby: 5mW (typ.)

IDT7007L

Active:850mW(typ.)

Standby: 1mW (typ.)

IDT7007 easily expands data bus width to 16 bits or more

◆

FunctionalBlockDiagram

OER

OEL

R/W

I/O0L- I/O7L

I/O0R-I/O7R

I/O

Control

(1,2)

BUSY ^(1,2)

BUSY

14R

14L

Address

Decoder

MEMORY

ARRAY

Address

Decoder

A0R

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

R/W

SEM

INT

SEM

M/S

INT ⁽²⁾

(2)

2940 drw 01

NOTES:

1. (MASTER): BUSY is output; (SLAVE): BUSY is input.

2. BUSY and INT outputs are non-tri-stated push-pull.

JUNE 1999

DSC 2940/8

12 3 4 5 6 7...21

中文翻译

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