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IDT6116SA35YG PDF预览

IDT6116SA35YG

更新时间: 2023-02-26 14:07:21
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
12页 137K
描述
Standard SRAM, 2KX8, 35ns, CMOS, PDSO24, 0.300 INCH, SOJ-24

IDT6116SA35YG 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOJ包装说明:0.300 INCH, SOJ-24
针数:24Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.82最长访问时间:35 ns
I/O 类型:COMMONJESD-30 代码:R-PDSO-J24
JESD-609代码:e3长度:15.88 mm
内存密度:16384 bit内存集成电路类型:STANDARD SRAM
内存宽度:8功能数量:1
端口数量:1端子数量:24
字数:2048 words字数代码:2000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:2KX8
输出特性:3-STATE可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:SOJ
封装等效代码:SOJ24,.34封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:5 V
认证状态:Not Qualified座面最大高度:3.76 mm
最大待机电流:0.002 A最小待机电流:4.5 V
子类别:SRAMs最大压摆率:0.08 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:J BEND
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.62 mm

IDT6116SA35YG 数据手册

 浏览型号IDT6116SA35YG的Datasheet PDF文件第2页浏览型号IDT6116SA35YG的Datasheet PDF文件第3页浏览型号IDT6116SA35YG的Datasheet PDF文件第4页浏览型号IDT6116SA35YG的Datasheet PDF文件第5页浏览型号IDT6116SA35YG的Datasheet PDF文件第6页浏览型号IDT6116SA35YG的Datasheet PDF文件第7页 
CMOS Static RAM  
16K (2K x 8-Bit)  
IDT6116SA  
IDT6116LA  
Features  
Description  
High-speed access and chip select times  
The IDT6116SA/LA is a 16,384-bit high-speed static RAM  
organized as 2K x 8. It is fabricated using IDT's high-performance,  
high-reliabilityCMOStechnology.  
Military:20/25/35/45/55/70/90/120/150ns(max.)  
Industrial:20/25/35/45ns(max.)  
– Commercial:15/20/25/35/45ns(max.)  
Low-power consumption  
Battery backup operation  
– 2V data retention voltage (LA version only)  
Produced with advanced CMOS high-performance  
technology  
CMOS process virtually eliminates alpha particle soft-error consumesonly1µWto4µWoperatingoffa2Vbattery.  
Access times as fastas 15ns are available. The circuitalsooffers a  
reduced power standby mode. When CS goes HIGH, the circuit will  
automatically go to, and remain in, a standby power mode, as long  
as CS remains HIGH. This capability provides significant system level  
power and cooling savings. The low-power (LA) version also offers a  
battery backup data retention capability where the circuit typically  
rates  
AllinputsandoutputsoftheIDT6116SA/LAareTTL-compatible.Fully  
static asynchronous circuitry is used, requiring no clocks or refreshing  
foroperation.  
TheIDT6116SA/LAispackagedin24-pin600and300milplasticor  
ceramicDIP,24-leadgull-wingSOIC,and24-leadJ-bendSOJproviding  
highboard-levelpackingdensities.  
Input and output directly TTL-compatible  
Static operation: no clocks or refresh required  
Available in ceramic and plastic 24-pin DIP, 24-pin Thin Dip,  
24-pin SOIC and 24-pin SOJ  
Military product compliant to MIL-STD-833, Class B  
Military grade product is manufactured in compliance to the latest  
version of MIL-STD-883, Class B, making it ideally suited to military  
temperatureapplicationsdemandingthehighestlevelofperformanceand  
reliability.  
FunctionalBlockDiagram  
A
0
CC  
V
128 X 128  
MEMORY  
ARRAY  
ADDRESS  
DECODER  
GND  
A 10  
0
I/O  
I/O CONTROL  
INPUT  
DATA  
CIRCUIT  
I/O7  
,
CS  
OE  
WE  
CONTROL  
CIRCUIT  
3089 drw 01  
NOVEMBER 2006  
1
©2006 IntegratedDeviceTechnology,Inc.  
DSC-3089/06  

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