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IDT6116SA20Y8 PDF预览

IDT6116SA20Y8

更新时间: 2024-11-10 10:13:23
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器光电二极管
页数 文件大小 规格书
11页 235K
描述
Standard SRAM, 2KX8, 20ns, CMOS, PDSO24, 0.300 INCH, SOJ-24

IDT6116SA20Y8 数据手册

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CMOS Static RAM  
16K (2K x 8-Bit)  
IDT6116SA  
IDT6116LA  
Features  
Description  
The IDT6116SA/LA is a 16,384-bit high-speed static RAM  
organized as 2K x 8. It is fabricated using IDT's high-performance,  
high-reliabilityCMOStechnology.  
High-speed access and chip select times  
Military:20/25/35/45/55/70/90/120/150ns(max.)  
Industrial:20/25/35/45ns(max.)  
– Commercial:15/20/25/35/45ns(max.)  
Low-power consumption  
Battery backup operation  
– 2V data retention voltage (LA version only)  
Produced with advanced CMOS high-performance  
technology  
CMOS process virtually eliminates alpha particle soft-error consumesonly1µWto4µWoperatingoffa2Vbattery.  
Access times as fastas 15ns are available. The circuitalsooffers a  
reduced power standby mode. When CS goes HIGH, the circuit will  
automatically go to, and remain in, a standby power mode, as long  
as CS remains HIGH. This capability provides significant system level  
power and cooling savings. The low-power (LA) version also offers a  
battery backup data retention capability where the circuit typically  
rates  
AllinputsandoutputsoftheIDT6116SA/LAareTTL-compatible.Fully  
static asynchronous circuitry is used, requiring no clocks or refreshing  
foroperation.  
TheIDT6116SA/LAispackagedin24-pin600and300milplasticor  
ceramicDIP,24-leadgull-wingSOIC,and24-leadJ-bendSOJproviding  
highboard-levelpackingdensities.  
Input and output directly TTL-compatible  
Static operation: no clocks or refresh required  
Available in ceramic and plastic 24-pin DIP, 24-pin Thin Dip,  
24-pin SOIC and 24-pin SOJ  
Military product compliant to MIL-STD-833, Class B  
Military grade product is manufactured in compliance to the latest  
version of MIL-STD-883, Class B, making it ideally suited to military  
temperatureapplicationsdemandingthehighestlevelofperformanceand  
reliability.  
FunctionalBlockDiagram  
A 0  
CC  
V
128 X 128  
MEMORY  
ARRAY  
ADDRESS  
DECODER  
GND  
A 10  
0
I/O  
I/O CONTROL  
INPUT  
DATA  
CIRCUIT  
I/O7  
,
CS  
CONTROL  
CIRCUIT  
OE  
WE  
3089 drw 01  
MARCH 2005  
1
©2005 IntegratedDeviceTechnology,Inc.  
DSC-3089/05  

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