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IDT5V993A-5QG PDF预览

IDT5V993A-5QG

更新时间: 2024-09-24 13:08:39
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器
页数 文件大小 规格书
8页 112K
描述
PLL Based Clock Driver, 5V Series, 8 True Output(s), 0 Inverted Output(s), PDSO28, LEAD FREE, QSOP-28

IDT5V993A-5QG 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:LEAD FREE, QSOP-28针数:28
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.7Is Samacsys:N
系列:5V输入调节:STANDARD
JESD-30 代码:R-PDSO-G28JESD-609代码:e3
长度:9.906 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:28实输出次数:8
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.7 ns座面最大高度:1.7272 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:3.9116 mm最小 fmax:85 MHz
Base Number Matches:1

IDT5V993A-5QG 数据手册

 浏览型号IDT5V993A-5QG的Datasheet PDF文件第2页浏览型号IDT5V993A-5QG的Datasheet PDF文件第3页浏览型号IDT5V993A-5QG的Datasheet PDF文件第4页浏览型号IDT5V993A-5QG的Datasheet PDF文件第5页浏览型号IDT5V993A-5QG的Datasheet PDF文件第6页浏览型号IDT5V993A-5QG的Datasheet PDF文件第7页 
RANGES  
3.3V PROGRAMMABLE SKEW  
PLL CLOCK DRIVER  
TURBOCLOCK™  
IDT5V993A  
NRND  
FEATURES:  
DESCRIPTION:  
• Ref input is 5V tolerant  
The IDT5V993A is a high fanout 3.3V PLL based clock driver  
intended for high performance computing and data-communications  
applications. A key feature of the programmable skew is the ability of  
outputs to lead or lag the REF input signal. The IDT5V993A has six  
programmable skew outputs and two zero skew outputs. Skew is  
controlled by 3-level input signals that may be hard-wired to appropri-  
ate HIGH-MID-LOW levels.  
• 3 pairs of programmable skew outputs  
• Low skew: 200ps same pair, 250ps all outputs  
• Selectable positive or negative edge synchronization:  
Excellent for DSP applications  
• Synchronous output enable  
• Output frequency: 3.75MHz to 85MHz  
• 2x, 4x, 1/2, and 1/4 outputs  
When the GND/sOE pin is held low, all the outputs are synchro-  
nously enabled. However, if GND/sOE is held high, all the outputs  
except 3Q0 and 3Q1 are synchronously disabled.  
• 3 skew grades:  
IDT5V993A-2: tSKEW0<250ps  
IDT5V993A-5: tSKEW0<500ps  
IDT5V993A-7: tSKEW0<750ps  
Furthermore, when the VCCQ/PE is held high, all the outputs are  
synchronized with the positive edge of the REF clock input. When  
VCCQ/PE is held low, all the outputs are synchronized with the negative  
edge of REF. Both devices have LVTTL outputs with 12mA balanced  
drive outputs.  
• 3-level inputs for skew and PLL range control  
• PLL bypass for DC testing  
• External feedback, internal loop filter  
• 12mA balanced drive outputs  
• Low Jitter: <200ps peak-to-peak  
• Available in QSOP package  
• Not Recommended for New Design  
FUNCTIONAL BLOCK DIAGRAM  
GND/sOE  
1Q0  
Skew  
Select  
1Q1  
3
3
3
3
1F1:0  
2F1:0  
3F1:0  
VCCQ/PE  
2Q0  
2Q1  
Skew  
Select  
3
REF  
PLL  
FB  
3Q0  
3Q1  
Skew  
Select  
3
3
FS  
4Q0  
4Q1  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
JULY 2012  
1
c
2012 Integrated Device Technology, Inc.  
DSC 5408/3  

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