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IDT5V9351 PDF预览

IDT5V9351

更新时间: 2024-11-26 22:20:31
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器
页数 文件大小 规格书
10页 79K
描述
LOW VOLTAGE PLL CLOCK DRIVER

IDT5V9351 数据手册

 浏览型号IDT5V9351的Datasheet PDF文件第2页浏览型号IDT5V9351的Datasheet PDF文件第3页浏览型号IDT5V9351的Datasheet PDF文件第4页浏览型号IDT5V9351的Datasheet PDF文件第5页浏览型号IDT5V9351的Datasheet PDF文件第6页浏览型号IDT5V9351的Datasheet PDF文件第7页 
LOW VOLTAGE PLL  
CLOCK DRIVER  
IDT5V9351  
FEATURES:  
DESCRIPTION:  
• Fully integrated PLL  
The IDT5V9351 is a high performance, zero delay, low skew, phase-lock  
loop (PLL) clock driver. It has four banks of configurable outputs. The  
IDT5V9351usesadifferentialPECLreferenceinputandanexternalfeedback  
input. These features allow the IDT5V9351 to be used as a zero delay, low  
skewfan-outbuffer. REF_SELallowsselectionbetweenPECLinputorTCLK,  
a CMOS clock driver input.  
• Output frequency up to 200MHz  
• 2.5V and 3.3V Compatible  
• Compatible with PowerPC™, Intel, and high performance RISC  
microprocessors  
• Output frequency configurable  
• Cycle-to-cycle jitter max. 22ps RMS  
• Compatible with MPC9351  
IfPLL_ENissettolowandREF_SELtohigh,itwillbypassthePLL. Bydoing  
so,theIDT5V9351willbeinclockbuffermode. AnyclockappliedtoTCLKwill  
be divided down to four output banks.  
• Available in TQFP package  
WhenPLL_ENissethigh, PLLisenabled. AnyclockappliedtoTCLKwill  
beclockedinbothphaseandfrequencytoFBIN. PECLclockisactivatedby  
settingREF_SELtolow.  
FUNCTIONALBLOCKDIAGRAM  
(pullup)  
PECL_CLK  
0
0
1
PECL_CLK  
÷2  
÷4  
÷8  
0
1
REF  
(pulldown)  
D
D
D
D
Q
Q
Q
Q
1
QA  
tCLK  
REF_SEL  
FBIN  
(pulldown)  
(pulldown)  
PLL  
FB  
200 - 400MHz  
0
1
QB  
(pullup)  
PLL_En  
QC0  
QC1  
0
1
(pulldown)  
fSELA  
fSELB  
fSELC  
fSELD  
(pulldown)  
(pulldown)  
QD0  
QD1  
QD2  
QD3  
QD4  
0
1
(pulldown)  
(pulldown)  
OE  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
MARCH 2003  
1
© 2003 Integrated Device Technology, Inc.  
DSC-5972/16  

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