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IDT54FCT833ALB PDF预览

IDT54FCT833ALB

更新时间: 2024-11-07 22:13:51
品牌 Logo 应用领域
艾迪悌 - IDT 总线收发器
页数 文件大小 规格书
8页 75K
描述
FAST CMOS PARITY BUS TRANSCEIVER

IDT54FCT833ALB 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QLCC包装说明:QCCN, LCC28,.45SQ
针数:28Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.49
其他特性:INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; PARITY GENERATION A TO B; ERROR DETECTION B TO A控制类型:INDEPENDENT CONTROL
计数方向:BIDIRECTIONAL系列:FCT
JESD-30 代码:S-CQCC-N28JESD-609代码:e0
长度:11.4554 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS TRANSCEIVER最大I(ol):0.032 A
位数:8功能数量:1
端口数量:2端子数量:28
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QCCN
封装等效代码:LCC28,.45SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):225
电源:5 VProp。Delay @ Nom-Sup:20 ns
传播延迟(tpd):14 ns认证状态:Not Qualified
筛选级别:38535Q/M;38534H;883B座面最大高度:2.54 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
翻译:N/A触发器类型:POSITIVE EDGE
宽度:11.4554 mm

IDT54FCT833ALB 数据手册

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IDT54/74FCT833A  
IDT54/74FCT833B  
FAST CMOS  
PARITY BUS  
TRANSCEIVER  
Integrated Device Technology, Inc.  
FEATURES:  
DESCRIPTION:  
• Equivalent to AMD’s Am29833 bipolar parity bus  
transceiver in pinout/function, speed and output drive  
over full temperature and voltage supply extremes  
• High-speed bidirectional bus transceiver for processor-  
organized devices  
The IDT54/74FCT833s are high-performance bus  
transceivers designed for two-way communications. They  
eachcontainan8-bitdatapathfromtheR(port)totheT(port),  
an 8-bit data path from the T (port) to the R (port), and a 9-bit  
parity checker/generator. The error flag can be clocked and  
stored in a register and read at the ERR output. The clear  
(CLR) input is used to clear the error flag register.  
• IDT54/74FCT833A equivalent to Am29833A speed and  
output drive  
• IDT54/74FCT833B 30% faster than Am29833A  
• Buffered direction and three-state controls  
• Error flag with open-drain output  
• IOL = 48mA (commercial) and 32mA (military)  
• TTL input and output level compatible  
• CMOS output level compatible  
The output enables OET and OER are used to force the  
port outputs to the high-impedance state so that the device  
can drive bus lines directly. In addition, OER and OET can be  
used to force a parity error by enabling both lines  
simultaneously. This transmission of inverted parity gives the  
designer more system diagnostic capability. The devices are  
specified at 48mA and 32mA output sink current over the  
commercial and military temperature ranges, respectively.  
• Substantially lower input current levels than AMD’s  
bipolar Am29800 series (5µA max.)  
• Available in plastic DIP, CERDIP, LCC and SOIC  
• Product available in Radiation Tolerant and Radiation  
Enhanced versions  
• Military product compliant to MIL-STD-883, Class B  
FUNCTIONAL BLOCK DIAGRAM  
R
I
T
I
8
8
PARITY  
T
OE  
OE  
R
8
8
S
MUX  
9
9-BIT  
PARITY TREE  
D
Q
Q
ERR  
P
CP  
CLR  
CLK  
CLR  
2557 drw 01  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
MAY 1992  
1992 Integrated Device Technology, Inc.  
7.21  
DSC-4621/2  
1

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