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IDT54FCT825CLB PDF预览

IDT54FCT825CLB

更新时间: 2024-11-07 22:17:59
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
8页 190K
描述
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS

IDT54FCT825CLB 数据手册

 浏览型号IDT54FCT825CLB的Datasheet PDF文件第2页浏览型号IDT54FCT825CLB的Datasheet PDF文件第3页浏览型号IDT54FCT825CLB的Datasheet PDF文件第4页浏览型号IDT54FCT825CLB的Datasheet PDF文件第5页浏览型号IDT54FCT825CLB的Datasheet PDF文件第6页浏览型号IDT54FCT825CLB的Datasheet PDF文件第7页 
IDT54/74FCT821A/B/C  
IDT54/74FCT823A/B/C  
IDT54/74FCT824A/B/C  
IDT54/74FCT825A/B/C  
HIGH-PERFORMANCE  
CMOS BUS INTERFACE  
REGISTERS  
Integrated Device Technology, Inc.  
FEATURES:  
DESCRIPTION:  
The IDT54/74FCT800 series is built using an advanced  
dual metal CMOS technology.  
• Equivalent to AMD’s Am29821-25 bipolar registers in  
pinout/function, speed and output drive over full tem-  
perature and voltage supply extremes  
• IDT54/74FCT821A/823A/824A/825A equivalent to  
FAST speed  
• IDT54/74FCT821B/823B/824B/825B 25% faster than  
FAST  
• IDT54/74FCT821C/823C/824C/825C 40% faster than  
FAST  
The IDT54/74FCT820 series bus interface registers are  
designed to eliminate the extra packages required to buffer  
existing registers and provide extra data width for wider  
address/data paths or buses carrying parity. The IDT54/  
74FCT821 are buffered, 10-bit wide versions of the popular  
‘374 function. The IDT54/74FCT823 and IDT54/74FCT824  
are 9-bit wide buffered registers with Clock Enable (EN) and  
Clear (CLR) – ideal for parity bus interfacing in high-perform-  
ance microprogrammed systems. The IDT54/74FCT825 are  
8-bit buffered registers with all the ‘823 controls plus multiple  
enables (OE1, OE2, OE3) to allow multiuser control of the  
interface, e.g., CS, DMA and RD/WR. They are ideal for use  
as an output port requiring HIGH IOL/IOH.  
All of the IDT54/74FCT800 high-performance interface  
familyaredesignedforhigh-capacitanceloaddrivecapability,  
while providing low-capacitance bus loading at both inputs  
and outputs. All inputs have clamp diodes and all outputs are  
designed for low-capacitance bus loading in high-impedance  
state.  
• Buffered common Clock Enable (EN) and asynchronous  
Clear input (CLR)  
• IOL = 48mA (commercial) and 32mA (military)  
• Clamp diodes on all inputs for ringing suppression  
• CMOS power levels (1mW typ. static)  
• TTL input and output compatibility  
• CMOS output level compatible  
• Substantially lower input current levels than AMD’s  
bipolar Am29800 series (5µA max.)  
• Product available in Radiation Tolerant and Radiation  
Enhanced versions  
• Military product compliant to MIL-STD-883, Class B  
FUNCTIONAL BLOCK DIAGRAMS  
IDT54/74FCT821/823/825  
IDT54/74FCT824  
D0  
DN  
D0  
DN  
EN  
EN  
CLR  
CLR  
CL  
CL  
CL  
CL  
D
Q
Q
D
Q
Q
D
Q
Q
D
Q
Q
CP  
CP  
CP  
CP  
CP  
OE  
CP  
OE  
Y0  
YN  
Y0  
YN  
2608 cnv* 02  
2608 cnv* 01  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
FAST is a trademark of National Semiconductor Co.  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
MAY 1992  
1992 Integrated Device Technology, Inc.  
7.19  
DSC-4618/2  
1

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