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IDT54FCT623CTLB PDF预览

IDT54FCT623CTLB

更新时间: 2024-11-15 23:10:11
品牌 Logo 应用领域
艾迪悌 - IDT 总线收发器
页数 文件大小 规格书
6页 106K
描述
FAST CMOS OCTAL BUS TRANSCEIVERS (3-STATE)

IDT54FCT623CTLB 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QLCC包装说明:QCCN, LCC20,.35SQ
针数:20Reach Compliance Code:not_compliant
风险等级:5.92其他特性:WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
控制类型:INDEPENDENT CONTROL计数方向:BIDIRECTIONAL
系列:FCTJESD-30 代码:S-CQCC-N20
JESD-609代码:e0长度:8.89 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS TRANSCEIVER
最大I(ol):0.048 A位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:QCCN封装等效代码:LCC20,.35SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):225电源:5 V
Prop。Delay @ Nom-Sup:5.4 ns传播延迟(tpd):5.4 ns
认证状态:Not Qualified筛选级别:38535Q/M;38534H;883B
座面最大高度:2.54 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:NO LEAD
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30翻译:N/A
宽度:8.89 mmBase Number Matches:1

IDT54FCT623CTLB 数据手册

 浏览型号IDT54FCT623CTLB的Datasheet PDF文件第2页浏览型号IDT54FCT623CTLB的Datasheet PDF文件第3页浏览型号IDT54FCT623CTLB的Datasheet PDF文件第4页浏览型号IDT54FCT623CTLB的Datasheet PDF文件第5页浏览型号IDT54FCT623CTLB的Datasheet PDF文件第6页 
IDT54/74FCT623T/AT/CT  
FAST CMOS OCTAL  
BUS TRANSCEIVERS  
(3-STATE)  
Integrated Device Technology, Inc.  
DESCRIPTION  
FEATURES:  
The FCT623T/AT/CT is a non-inverting octal transceiver  
with 3-state bus-driving outputs in both the send and receive  
directions.TheBbusoutputsarecapableofsinking64mAand  
sourcing up to 15mA, providing very good capacitive drive  
characteristics.  
• Std., A and C speed grades  
• Low input and output leakage 1µA (max.)  
• CMOS power levels  
• True TTL input and output compatibility  
– VOH = 3.3V (typ.)  
These octal bus transceivers are designed for asynchro-  
noustwo-waycommunicationbetweendatabuses.Thecontrol  
function implementation allows for maximum flexibility in  
timing.  
One important feature of the FCT623T/AT/CT is the Power  
Down Disable capability. When the GAB and GBA inputs are  
conditioned to put the device in high-Z state, the I/O ports will  
maintain high impedance during power supply ramps and  
when VCC = 0V. This is a desirable feature in back-plane  
applications where it may be necessary to perform “live”  
insertion and removal of cards for on-line maintenance. It is  
also a benefit in systems with multiple redundancy where one  
or more redundant cards may be powered-off.  
– VOL = 0.3V (typ.)  
• High drive outputs (-15mA IOH, 64mA IOL)  
• Power off disable outputs permit “live insertion”  
• Meets or exceeds JEDEC standard 18 specifications  
• Product available in Radiation Tolerant and Radiation  
Enhanced versions  
• Military product compliant to MIL-STD-883, Class B  
and DESC listed (dual marked)  
• Available in DIP, SOIC, CERPACK and LCC packages  
FUNCTIONAL BLOCK DIAGRAM  
GBA  
GAB  
B1  
A1  
B2 - B8  
A2 - A8  
7 other transceivers  
2563 drw 01  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
NOVEMBER 1995  
1996 Integrated Device Technology, Inc.  
6.19  
DSC-2563/5  
1
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