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IDT54FCT273AT

更新时间: 2024-11-26 23:10:07
品牌 Logo 应用领域
艾迪悌 - IDT 触发器
页数 文件大小 规格书
7页 113K
描述
FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET

IDT54FCT273AT 数据手册

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IDT54/74FCT273T/AT/CT  
FAST CMOS  
OCTAL D FLIP-FLOP  
WITH MASTER RESET  
Integrated Device Technology, Inc.  
DESCRIPTION:  
FEATURES:  
The IDT54/74FCT273T/AT/CT are octal D flip-flops built  
using an advanced dual metal CMOS technology. The IDT54/  
74FCT273T/AT/CT have eight edge-triggered D-type flip-  
flops with individual D inputs and O outputs. The common  
buffered Clock (CP) and Master Reset (MR) inputs load and  
reset (clear) all flip-flops simultaneously.  
• Std., A, and C speed grades  
• Low input and output leakage 1µA (max.)  
• CMOS power levels  
• True TTL input and output compatibility  
– VOH = 3.3V (typ.)  
– VOL = 0.3V (typ.)  
The register is fully edge-triggered. The state of each D  
input, one set-up time before the LOW-to-HIGH clock  
transition, is transferred to the corresponding flip-flop’s O  
output.  
• High drive outputs (-15mA IOH, 48mA IOL)  
• Meets or exceeds JEDEC standard 18 specifications  
• Product available in Radiation Tolerant and Radiation  
Enhanced versions  
All outputs will be forced LOW independently of Clock or  
Data inputs by a LOW voltage level on the MR input. The  
device is useful for applications where the true output only is  
required and the Clock and Master Reset are common to all  
storage elements.  
• Military product compliant to MIL-STD-883, Class B  
and DESC listed (dual marked)  
• Available in DIP, SOIC, QSOP, CERPACK and LCC  
packages  
FUNCTIONAL BLOCK DIAGRAM  
D
0
D
1
D
2
D3  
D4  
D
5
D
6
D7  
CP  
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP  
CP  
CP  
CP  
CP  
CP  
CP  
CP  
R
D
R
D
RD  
RD  
R
D
R
D
RD  
RD  
MR  
O
0
O
1
O2  
O
3
O
4
O
5
O6  
O7  
2568 drw 03  
PIN CONFIGURATIONS  
INDEX  
1
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VCC  
O7  
D7  
MR  
O0  
2
3
4
3
2
20 19  
D0  
D1  
P20-1  
D20-1  
SO20-2  
SO20-8  
&
1
D
1
4
18  
D7  
D6  
O
1
2
5
6
7
8
17  
16  
15  
14  
D
6
O1  
O2  
D2  
D3  
5
O6  
O5  
O
O
6
5
L20-2  
6
D
2
3
O
7
D5  
D4  
E20-1  
D
D5  
8
9 10 11 12 13  
9
O3  
GND  
O4  
10  
CP  
2568 drw 01  
2568 drw 02  
DIP/SOIC/QSOP/CERPACK  
TOP VIEW  
LCC  
TOP VIEW  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
APRIL 1995  
1995 Integrated Device Technology, Inc.  
6.10  
DSC-4209/3  
1

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