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IDT54FCT162543ATEB PDF预览

IDT54FCT162543ATEB

更新时间： 2024-11-23 23:12:43
品牌 Logo 应用领域
艾迪悌 - IDT 总线驱动器总线收发器逻辑集成电路输出元件
页数 文件大小 规格书
8页 131K
描述
FAST CMOS 16-BIT LATCHED TRANSCEIVER

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中文翻译

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IDT54FCT162543ATEB 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DFP包装说明：DFP, FL56,.4,25
针数：56Reach Compliance Code：not_compliant
风险等级：5.5其他特性：INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; MASTER CONTROL FOR LATCH
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：FCTJESD-30 代码：R-GDFP-F56
JESD-609代码：e0长度：18.415 mm
负载电容（CL）：50 pF逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
最大I（ol）：0.016 A位数：8
功能数量：2端口数量：2
端子数量：56最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE WITH SERIES RESISTOR
输出极性：TRUE封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DFP封装等效代码：FL56,.4,25
封装形状：RECTANGULAR封装形式：FLATPACK
峰值回流温度（摄氏度）：225电源：5 V
Prop。Delay @ Nom-Sup：7.5 ns传播延迟（tpd）：9 ns
认证状态：Not Qualified筛选级别：MIL-STD-883 Class B
座面最大高度：2.413 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：FLAT
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30翻译：N/A
宽度：9.652 mmBase Number Matches：1

IDT54FCT162543ATEB 数据手册

 浏览型号IDT54FCT162543ATEB的Datasheet PDF文件第2页浏览型号IDT54FCT162543ATEB的Datasheet PDF文件第3页浏览型号IDT54FCT162543ATEB的Datasheet PDF文件第4页浏览型号IDT54FCT162543ATEB的Datasheet PDF文件第5页浏览型号IDT54FCT162543ATEB的Datasheet PDF文件第6页浏览型号IDT54FCT162543ATEB的Datasheet PDF文件第7页 
IDT54/74FCT16543T/AT/CT/ET  
IDT54/74FCT162543T/AT/CT/ET  
FAST CMOS  
16-BIT LATCHED  
TRANSCEIVER  
Integrated Device Technology, Inc.  
FEATURES:  
DESCRIPTION:  
• Common features:  
The FCT16543T/AT/CT/ET and FCT162543T/AT/CT/ET  
– 0.5 MICRON CMOS Technology  
– High-speed, low-power CMOS replacement for  
ABT functions  
– Typical tSK(o) (Output Skew) < 250ps  
– Low input and output leakage ≤1µA (max.)  
– ESD > 2000V per MIL-STD-883, Method 3015;  
> 200V using machine model (C = 200pF, R = 0)  
– Packages include 25 mil pitch SSOP, 19.6 mil pitch  
16-bit latched transceivers are built using advanced dual metal  
CMOS technology. These high-speed, low-power devices are  
organized as two independent 8-bit D-type latched transceiv-  
ers with separate input and output control to permit indepen-  
dent control of data flow in either direction. For example, the A-  
to-B Enable (xCEAB) must be LOW in order to enter data from  
the A port or to output data from the B port. xLEABcontrols the  
latch function. When xLEAB is LOW, the latches are transpar-  
TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack ent. A subsequent LOW-to-HIGH transition of xLEAB signal  
– Extended commercial range of -40°C to +85°C  
– VCC = 5V ±10%  
putstheAlatchesinthestoragemode. xOEABperformsoutput  
enable function on the B port. Data flow from the B port to the  
A port is similar but requires using xCEBA, xLEBA, and xOEBA  
inputs. Flow-through organization of signal pins simplifies  
layout. All inputs are designed with hysteresis for improved  
noise margin.  
The FCT16543T/AT/CT/ET are ideally suited for driving  
high-capacitance loads and low-impedance backplanes. The  
output buffers are designed with power off disable capability to  
allow"liveinsertion"ofboardswhenusedasbackplanedrivers.  
The FCT162543T/AT/CT/ET have balanced output drive  
with current limiting resistors. This offers low ground bounce,  
minimal undershoot, and controlled output fall times–reducing  
the need for external series terminating resistors. The  
FCT162543T/AT/CT/ET are plug-in replacements for the  
FCT16543T/AT/CT/ET and 54/74ABT16543 for on-board bus  
interface applications.  
• Features for FCT16543T/AT/CT/ET:  
– High drive outputs (-32mA IOH, 64mA IOL)  
– Power off disable outputs permit “live insertion”  
– Typical VOLP (Output Ground Bounce) < 1.0V at  
VCC = 5V, TA = 25°C  
• Features for FCT162543T/AT/CT/ET:  
– Balanced Output Drivers: ±24mA (commercial),  
±16mA (military)  
– Reduced system switching noise  
– Typical VOLP (Output Ground Bounce) < 0.6V at  
VCC = 5V,TA = 25°C  
FUNCTIONAL BLOCK DIAGRAM  
2OEBA  
2CEBA  
1
OEBA  
CEBA  
LEBA  
OEAB  
CEAB  
LEAB  
1
2LEBA  
2OEAB  
2CEAB  
1
1
1
2LEAB  
1
C
C
D
2A1  
1A1  
2B1  
D
1B1  
C
D
C
D
TO 7 OTHER CHANNELS  
TO 7 OTHER CHANNELS  
2618 drw 02  
2618 drw 01  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
SEPTEMBER 1996  
1996 Integrated Device Technology, Inc.  
5.12  
DSC-2618/7  
1
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中文翻译

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