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IDT54FCT162511CTPFB PDF预览

IDT54FCT162511CTPFB

更新时间: 2024-11-23 23:12:43
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
11页 208K
描述
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY

IDT54FCT162511CTPFB 数据手册

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IDT54/74FCT162511AT/CT  
FAST CMOS 16-BIT  
REGISTERED/LATCHED  
TRANSCEIVER WITH PARITY  
Integrated Device Technology, Inc.  
FEATURES:  
• 0.5 MICRON CMOS Technology  
typelatchesandD-typeflip-flopstoallowdataflowintranspar-  
ent, latched or clocked modes. The device has a parity  
generator/cheker in the A-to-B direction and a parity checker  
in the B-to-A direction. Error checking is done at the byte level  
with separate parity bits for each byte. Separate error flags  
exits for each direction with a single error flag indicating an  
error for either byte in the A-to-B direction and a second error  
flag indicating an error for either byte in the B-to-A direction.  
The parity error flags are open drain outputs which can be tied  
together and/or tied with flags from other devices to form a  
single error flag or interrupt. The parity error flags are enabled  
by the OExx control pins allowing the designer to disable the  
error flag during combinational transitions.  
• Typical tsk(o) (Output Skew) < 250ps, clocked mode  
• Low input and output leakage 1µA (max)  
• ESD > 2000V per MIL-STD-883, Method 3015;  
> 200V using machine model (C = 200pF, R = 0)  
• Packagesinclude25milpitchSSOP,19.6milpitchTSSOP,  
15.7 mil pitch TVSOP and 25 mil pitch Cerpack  
• Extended commercial range of –40°C to +85°C  
• VCC = 5V ±10%  
• Balanced Output Drivers:  
±24mA (commercial)  
±16mA (military)  
• Series current limiting resistors  
The control pins LEAB, CLKAB and OEAB control opera-  
tion in the A-to-B direction while LEBA, CLKBA and OEBA  
controltheB-to-Adirection. GEN/CHKisonlyfortheselection  
of A-to-B operation, the B-to-A direction is always in checking  
mode. The ODD/EVEN select is common between the two  
directions. Except for the ODD/EVEN control, independent  
operation can be achieved between the two directions by  
using the corresponding control lines.  
• Generate/Check, Check/Check modes  
• Open drain parity error allows wire-OR  
DESCRIPTION:  
TheFCT162511AT/CT16-bitregistered/latchedtransceiver  
with parity is built using advanced dual metal CMOS technol-  
ogy. This high-speed, low-power transceiver combines D-  
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM:  
LEAB  
CLKAB  
Data  
OEAB  
Parity, data  
B0-15  
16  
18  
PB1,2  
Parity  
Latch/  
Register  
GEN/CHK  
2
Byte  
Parity  
PERB  
Generator/  
Checker  
A0-15  
PA1,2  
(Open Drain)  
ODD/EVEN  
LEBA  
CLKBA  
Parity, Data  
Parity, data  
18  
18  
Latch/  
Register  
OEBA  
Byte  
Parity  
Checking  
PERA  
(Open Drain)  
2916 drw 01  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
AUGUST 1996  
1996 Integrated Device Technology, Inc.  
5.11  
DSC–2916/5  
1

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