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IDT54FCT162511CTEB PDF预览

IDT54FCT162511CTEB

更新时间： 2024-11-19 23:12:43
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
11页 208K
描述
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY

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中文翻译

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IDT54FCT162511CTEB 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DFP包装说明：CERPACK-56
针数：56Reach Compliance Code：not_compliant
风险等级：5.88其他特性：INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; PARITY GENERATION/ERROR DETECTION A TO B
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：FCTJESD-30 代码：R-GDFP-F56
JESD-609代码：e0长度：18.415 mm
负载电容（CL）：50 pF逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
最大I（ol）：0.016 A位数：16
功能数量：1端口数量：2
端子数量：56最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE WITH SERIES RESISTOR
输出极性：TRUE封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DFP封装等效代码：FL56,.4,25
封装形状：RECTANGULAR封装形式：FLATPACK
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
Prop。Delay @ Nom-Sup：4.5 ns传播延迟（tpd）：5.5 ns
认证状态：Not Qualified筛选级别：MIL-STD-883 Class B
座面最大高度：2.413 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：FLAT
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
触发器类型：POSITIVE EDGE宽度：9.652 mm
Base Number Matches：1

IDT54FCT162511CTEB 数据手册

 浏览型号IDT54FCT162511CTEB的Datasheet PDF文件第2页浏览型号IDT54FCT162511CTEB的Datasheet PDF文件第3页浏览型号IDT54FCT162511CTEB的Datasheet PDF文件第4页浏览型号IDT54FCT162511CTEB的Datasheet PDF文件第5页浏览型号IDT54FCT162511CTEB的Datasheet PDF文件第6页浏览型号IDT54FCT162511CTEB的Datasheet PDF文件第7页 
IDT54/74FCT162511AT/CT  
FAST CMOS 16-BIT  
REGISTERED/LATCHED  
TRANSCEIVER WITH PARITY  
Integrated Device Technology, Inc.  
FEATURES:  
• 0.5 MICRON CMOS Technology  
typelatchesandD-typeflip-flopstoallowdataflowintranspar-  
ent, latched or clocked modes. The device has a parity  
generator/cheker in the A-to-B direction and a parity checker  
in the B-to-A direction. Error checking is done at the byte level  
with separate parity bits for each byte. Separate error flags  
exits for each direction with a single error flag indicating an  
error for either byte in the A-to-B direction and a second error  
flag indicating an error for either byte in the B-to-A direction.  
The parity error flags are open drain outputs which can be tied  
together and/or tied with flags from other devices to form a  
single error flag or interrupt. The parity error flags are enabled  
by the OExx control pins allowing the designer to disable the  
error flag during combinational transitions.  
• Typical tsk(o) (Output Skew) < 250ps, clocked mode  
• Low input and output leakage ≤1µA (max)  
• ESD > 2000V per MIL-STD-883, Method 3015;  
> 200V using machine model (C = 200pF, R = 0)  
• Packagesinclude25milpitchSSOP,19.6milpitchTSSOP,  
15.7 mil pitch TVSOP and 25 mil pitch Cerpack  
• Extended commercial range of –40°C to +85°C  
• VCC = 5V ±10%  
• Balanced Output Drivers:  
±24mA (commercial)  
±16mA (military)  
• Series current limiting resistors  
The control pins LEAB, CLKAB and OEAB control opera-  
tion in the A-to-B direction while LEBA, CLKBA and OEBA  
controltheB-to-Adirection. GEN/CHKisonlyfortheselection  
of A-to-B operation, the B-to-A direction is always in checking  
mode. The ODD/EVEN select is common between the two  
directions. Except for the ODD/EVEN control, independent  
operation can be achieved between the two directions by  
using the corresponding control lines.  
• Generate/Check, Check/Check modes  
• Open drain parity error allows wire-OR  
DESCRIPTION:  
TheFCT162511AT/CT16-bitregistered/latchedtransceiver  
with parity is built using advanced dual metal CMOS technol-  
ogy. This high-speed, low-power transceiver combines D-  
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM:  
LEAB  
CLKAB  
Data  
OEAB  
Parity, data  
B0-15  
16  
18  
PB1,2  
Parity  
Latch/  
Register  
GEN/CHK  
2
Byte  
Parity  
PERB  
Generator/  
Checker  
A0-15  
PA1,2  
(Open Drain)  
ODD/EVEN  
LEBA  
CLKBA  
Parity, Data  
Parity, data  
18  
18  
Latch/  
Register  
OEBA  
Byte  
Parity  
Checking  
PERA  
(Open Drain)  
2916 drw 01  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
AUGUST 1996  
1996 Integrated Device Technology, Inc.  
5.11  
DSC–2916/5  
1
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