5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> IDT54FCT162511ATEB
IDT54FCT162511ATEB PDF预览

IDT54FCT162511ATEB

更新时间： 2024-11-19 23:12:43
品牌 Logo 应用领域
艾迪悌 - IDT 总线驱动器总线收发器触发器逻辑集成电路输出元件
页数 文件大小 规格书
11页 208K
描述
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY

阅读下载

中文翻译

获取价格

IDT54FCT162511ATEB 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DFP包装说明：CERPACK-56
针数：56Reach Compliance Code：not_compliant
风险等级：5.89Is Samacsys：N
其他特性：INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; PARITY GENERATION/ERROR DETECTION A TO B控制类型：INDEPENDENT CONTROL
计数方向：BIDIRECTIONAL系列：FCT
JESD-30 代码：R-GDFP-F56JESD-609代码：e0
长度：18.415 mm负载电容（CL）：50 pF
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER最大I（ol）：0.016 A
位数：16功能数量：1
端口数量：2端子数量：56
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE WITH SERIES RESISTOR输出极性：TRUE
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DFP
封装等效代码：FL56,.4,25封装形状：RECTANGULAR
封装形式：FLATPACK峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 VProp。Delay @ Nom-Sup：5.3 ns
传播延迟（tpd）：6 ns认证状态：Not Qualified
筛选级别：MIL-STD-883 Class B座面最大高度：2.413 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：FLAT端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A触发器类型：POSITIVE EDGE
宽度：9.652 mmBase Number Matches：1

IDT54FCT162511ATEB 数据手册

 浏览型号IDT54FCT162511ATEB的Datasheet PDF文件第2页浏览型号IDT54FCT162511ATEB的Datasheet PDF文件第3页浏览型号IDT54FCT162511ATEB的Datasheet PDF文件第4页浏览型号IDT54FCT162511ATEB的Datasheet PDF文件第5页浏览型号IDT54FCT162511ATEB的Datasheet PDF文件第6页浏览型号IDT54FCT162511ATEB的Datasheet PDF文件第7页 
IDT54/74FCT162511AT/CT  
FAST CMOS 16-BIT  
REGISTERED/LATCHED  
TRANSCEIVER WITH PARITY  
Integrated Device Technology, Inc.  
FEATURES:  
• 0.5 MICRON CMOS Technology  
typelatchesandD-typeflip-flopstoallowdataflowintranspar-  
ent, latched or clocked modes. The device has a parity  
generator/cheker in the A-to-B direction and a parity checker  
in the B-to-A direction. Error checking is done at the byte level  
with separate parity bits for each byte. Separate error flags  
exits for each direction with a single error flag indicating an  
error for either byte in the A-to-B direction and a second error  
flag indicating an error for either byte in the B-to-A direction.  
The parity error flags are open drain outputs which can be tied  
together and/or tied with flags from other devices to form a  
single error flag or interrupt. The parity error flags are enabled  
by the OExx control pins allowing the designer to disable the  
error flag during combinational transitions.  
• Typical tsk(o) (Output Skew) < 250ps, clocked mode  
• Low input and output leakage ≤1µA (max)  
• ESD > 2000V per MIL-STD-883, Method 3015;  
> 200V using machine model (C = 200pF, R = 0)  
• Packagesinclude25milpitchSSOP,19.6milpitchTSSOP,  
15.7 mil pitch TVSOP and 25 mil pitch Cerpack  
• Extended commercial range of –40°C to +85°C  
• VCC = 5V ±10%  
• Balanced Output Drivers:  
±24mA (commercial)  
±16mA (military)  
• Series current limiting resistors  
The control pins LEAB, CLKAB and OEAB control opera-  
tion in the A-to-B direction while LEBA, CLKBA and OEBA  
controltheB-to-Adirection. GEN/CHKisonlyfortheselection  
of A-to-B operation, the B-to-A direction is always in checking  
mode. The ODD/EVEN select is common between the two  
directions. Except for the ODD/EVEN control, independent  
operation can be achieved between the two directions by  
using the corresponding control lines.  
• Generate/Check, Check/Check modes  
• Open drain parity error allows wire-OR  
DESCRIPTION:  
TheFCT162511AT/CT16-bitregistered/latchedtransceiver  
with parity is built using advanced dual metal CMOS technol-  
ogy. This high-speed, low-power transceiver combines D-  
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM:  
LEAB  
CLKAB  
Data  
OEAB  
Parity, data  
B0-15  
16  
18  
PB1,2  
Parity  
Latch/  
Register  
GEN/CHK  
2
Byte  
Parity  
PERB  
Generator/  
Checker  
A0-15  
PA1,2  
(Open Drain)  
ODD/EVEN  
LEBA  
CLKBA  
Parity, Data  
Parity, data  
18  
18  
Latch/  
Register  
OEBA  
Byte  
Parity  
Checking  
PERA  
(Open Drain)  
2916 drw 01  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
AUGUST 1996  
1996 Integrated Device Technology, Inc.  
5.11  
DSC–2916/5  
1
1234567...11

中文翻译

下载PDF

与IDT54FCT162511ATEB相关器件

型号 品牌 获取价格 描述 数据表
IDT54FCT162511ATPA IDT

获取价格

 		FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY
IDT54FCT162511ATPAB IDT

获取价格

 		FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY
IDT54FCT162511ATPF IDT

获取价格

 		FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY
IDT54FCT162511ATPFB IDT

获取价格

 		FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY
IDT54FCT162511ATPV IDT

获取价格

 		FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY
IDT54FCT162511ATPVB IDT

获取价格

 		FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY
IDT54FCT162511CT IDT

获取价格

 		FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY
IDT54FCT162511CTE IDT

获取价格

 		FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY
IDT54FCT162511CTEB IDT

获取价格

 		FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY
IDT54FCT162511CTPA IDT

获取价格

 		FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY

与IDT54FCT162511ATEB相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证