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IDT54FCT162500ETEB PDF预览

IDT54FCT162500ETEB

更新时间： 2024-11-19 23:12:43
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
8页 126K
描述
FAST CMOS 18-BIT REGISTERED TRANSCEIVER

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中文翻译

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IDT54FCT162500ETEB 技术参数

生命周期：Obsolete零件包装代码：DFP
包装说明：DFP,针数：56
Reach Compliance Code：unknown风险等级：5.84
其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION系列：FCT
JESD-30 代码：R-GDFP-F56JESD-609代码：e0
长度：18.415 mm逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
位数：18功能数量：1
端口数量：2端子数量：56
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE WITH SERIES RESISTOR输出极性：TRUE
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DFP
封装形状：RECTANGULAR封装形式：FLATPACK
认证状态：Not Qualified座面最大高度：2.143 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：TIN LEAD端子形式：FLAT
端子节距：0.635 mm端子位置：DUAL
宽度：9.652 mmBase Number Matches：1

IDT54FCT162500ETEB 数据手册

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IDT54/74FCT16500AT/CT/ET  
IDT54/74FCT162500AT/CT/ET  
FAST CMOS  
18-BIT REGISTERED  
TRANSCEIVER  
Integrated Device Technology, Inc.  
bitregisteredtransceiversarebuiltusingadvanceddualmetal  
CMOS technology. These high-speed, low-power 18-bit reg-  
istered bus transceivers combine D-type latches and D-type  
flip-flopstoallowdataflowintransparent, latchedandclocked  
modes. Data flow in each direction is controlled by output-  
enable (OEAB and OEBA), latch enable (LEAB and LEBA)  
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow,  
thedeviceoperatesintransparentmodewhenLEABisHIGH.  
When LEAB is LOW, the A data is latched if CLKAB is held at  
a HIGH or LOW logic level. If LEAB is LOW, the A bus data is  
stored in the latch/flip-flop on the HIGH-to-LOW transition of  
CLKAB. OEAB performs the output enable function on the B  
port. Data flow from B port to A port is similar but uses OEBA,  
LEBA and CLKBA. Flow-through organization of signal pins  
simplifies layout. All inputs are designed with hysteresis for  
improved noise margin.  
FEATURES:  
• Common features:  
– 0.5 MICRON CMOS Technology  
– High-speed, low-power CMOS replacement for  
ABT functions  
– Typical tSK(o) (Output Skew) < 250ps  
– Low input and output leakage ≤1µA (max.)  
– ESD > 2000V per MIL-STD-883, Method 3015;  
> 200V using machine model (C = 200pF, R = 0)  
– Packages include 25 mil pitch SSOP, 19.6 mil pitch  
TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack  
– Extended commercial range of -40°C to +85°C  
– VCC = 5V ±10%  
• Features for FCT16500AT/CT/ET:  
– High drive outputs (-32mA IOH, 64mA IOL)  
– Power off disable outputs permit “live insertion”  
– Typical VOLP (Output Ground Bounce) < 1.0V at  
VCC = 5V, TA = 25°C  
The FCT16500AT/CT/ET are ideally suited for driving  
high-capacitance loads and low-impedance backplanes. The  
output buffers are designed with power off disable capability  
to allow "live insertion" of boards when used as backplane  
drivers.  
• Features for FCT162500AT/CT/ET:  
– Balanced Output Drivers: ±24mA (commercial),  
±16mA (military)  
The FCT162500AT/CT/ET have balanced output drive  
with current limiting resistors. This offers low ground bounce,  
minimalundershoot,andcontrolledoutputfalltimes–reducing  
the need for external series terminating resistors. The  
FCT162500AT/CT/ET are plug-in replacements for the  
FCT16500AT/CT/ET and ABT16500 for on-board bus inter-  
face applications.  
– Reduced system switching noise  
– Typical VOLP (Output Ground Bounce) < 0.6V at  
VCC = 5V,TA = 25°C  
DESCRIPTION:  
The FCT16500AT/CT/ET and FCT162500AT/CT/ET 18-  
FUNCTIONAL BLOCK DIAGRAM  
OEAB  
CLKBA  
LEBA  
OEBA  
CLKAB  
LEAB  
C
C
B1  
D
D
A1  
C
D
C
D
TO 17 OTHER CHANNELS  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
2548 drw 01  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
AUGUST 1996  
1996 Integrated Device Technology, Inc.  
5.9  
DSC-2548/7  
1
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