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IDT2309-1DCI PDF预览

IDT2309-1DCI

更新时间: 2024-10-02 22:29:23
品牌 Logo 应用领域
艾迪悌 - IDT 时钟
页数 文件大小 规格书
10页 136K
描述
3.3V ZERO DELAY CLOCK BUFFER

IDT2309-1DCI 数据手册

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IDT2309  
3.3V ZERO DELAY  
CLOCK BUFFER  
FEATURES:  
DESCRIPTION:  
• Phase-Lock Loop Clock Distribution  
• 10MHz to 133MHz operating frequency  
• Distributes one clock input to one bank of five and one bankd  
of four outputs  
The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer,  
designedtoaddresshigh-speedclockdistributionapplications. Thezero  
delay is achieved by aligning the phase between the incoming clock and  
the output clock, operable within the range of 10 to 133MHz.  
TheIDT2309isa16-pinversionoftheIDT2305. TheIDT2309accepts  
one reference input, and drives two banks of four low skew clocks. The  
-1H version of this device operates at up to 133MHz frequency and has  
higher drive than the -1 device. All parts have on-chip PLLs which lock  
to an input clock on the REF pin. The PLL feedback is on-chip and is  
obtained from the CLKOUT pad. In the absence of an input clock, the  
IDT2309 enters power down, and the outputs are tri-stated. In this mode,  
• Separate output enable for each output bank  
• Output Skew < 250ps  
• Low jitter <200 ps cycle-to-cycle  
• IDT2309-1 for Standard Drive  
• IDT2309-1H for High Drive  
• No external RC network required  
• Operates at 3.3V VDD  
• Available in SOIC and TSSOP packages  
the device will draw less than 25µA.  
The IDT2309 is characterized for both Industrial and Commercial  
operation.  
NOTE: For new designs, refer to AN-233.  
FUNCTIONALBLOCKDIAGRAM  
16  
CLKOUT  
2
CLKA1  
PLL  
1
REF  
3
CLKA2  
14  
CLKA3  
15  
CLKA4  
8
S2  
Control  
Logic  
9
S1  
6
CLKB1  
7
CLKB2  
10  
CLKB3  
11  
CLKB4  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
NOVEMBER 2002  
1
c
2002 Integrated Device Technology, Inc.  
DSC 5175/5  

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