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IDT2305A-1DCI PDF预览

IDT2305A-1DCI

更新时间: 2024-10-03 04:15:27
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 53K
描述
3.3V ZERO DELAY CLOCK BUFFER

IDT2305A-1DCI 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP8,.25
针数:8Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.68
Is Samacsys:N系列:2305
输入调节:STANDARDJESD-30 代码:R-PDSO-G8
JESD-609代码:e0长度:4.9276 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER最大I(ol):0.008 A
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:8
实输出次数:4最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):240
电源:3.3 V传播延迟(tpd):0.35 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.25 ns
座面最大高度:1.7272 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
宽度:3.937 mm最小 fmax:133 MHz
Base Number Matches:1

IDT2305A-1DCI 数据手册

 浏览型号IDT2305A-1DCI的Datasheet PDF文件第2页浏览型号IDT2305A-1DCI的Datasheet PDF文件第3页浏览型号IDT2305A-1DCI的Datasheet PDF文件第4页浏览型号IDT2305A-1DCI的Datasheet PDF文件第5页浏览型号IDT2305A-1DCI的Datasheet PDF文件第6页浏览型号IDT2305A-1DCI的Datasheet PDF文件第7页 
IDT2305A  
3.3V ZERO DELAY CLOCK  
BUFFER  
FEATURES:  
DESCRIPTION:  
• Phase-Lock Loop Clock Distribution  
• 10MHz to 133MHz operating frequency  
• Distributes one clock input to one bank of five outputs  
• Zero Input-Output Delay  
The IDT2305A is a high-speed phase-lock loop (PLL) clock buffer,  
designed to address high-speed clock distribution applications. The zero  
delay is achieved by aligning the phase between the incoming clock and  
the output clock, operable within the range of 10 to 133MHz.  
• Output Skew < 250ps  
The IDT2305A is an 8-pin version of the IDT2309A. IDT2305A accepts  
one reference input, and drives out five low skew clocks. The -1H version  
ofthisdeviceoperatesupto133MHzfrequencyandhasahigherdrivethan  
the -1 device. All parts have on-chip PLLs which lock to an input clock on  
theREFpin.ThePLLfeedbackison-chipandisobtainedfromtheCLKOUT  
pad. In the absence of an input clock, the IDT2305A enters power down.  
• Low jitter <200 ps cycle-to-cycle  
• IDT2305A-1 for Standard Drive  
• IDT2305A-1H for High Drive  
• No external RC network required  
• Operates at 3.3V VDD  
• Power down mode  
• Available in SOIC package  
Inthismode,thedevicewilldrawlessthan1AforCommercialTempera-  
turerangeandlessthan2AforIndustrialtemperaturerange, theoutputs  
aretri-stated,andthePLLisnotrunning,resultinginasignificantreduction  
of power.  
The IDT2305A is characterized for both Industrial and Commercial  
operation.  
FUNCTIONALBLOCKDIAGRAM  
8
CLKOUT  
3
CLK1  
PLL  
1
Control  
Logic  
REF  
2
CLK2  
CLK3  
CLK4  
5
7
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
JULY 2004  
1
c
2004 Integrated Device Technology, Inc.  
DSC 6586/3  

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