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9ZX21901CKLF PDF预览

9ZX21901CKLF

更新时间: 2024-02-27 03:17:12
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器逻辑集成电路PC
页数 文件大小 规格书
16页 174K
描述
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI

9ZX21901CKLF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:VFQFPN
包装说明:HVQCCN,针数:72
Reach Compliance Code:compliant风险等级:5.73
Samacsys Description:VFQFP-N 10.0 X 10.0 X 0.9 MM - NO LEAD系列:9ZX
输入调节:DIFFERENTIAL MUXJESD-30 代码:S-XQCC-N72
JESD-609代码:e3长度:10 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:72实输出次数:38
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
座面最大高度:1 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10 mm
Base Number Matches:1

9ZX21901CKLF 数据手册

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DATASHEET  
9ZX21901C  
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
Description  
Features/Benefits  
The 9ZX21901 is Intel DB1900Z Differential Buffer suitable for PCI-  
Express Gen3 or QPI applications.The part is backwards compatible  
to PCIe Gen1 and Gen2. A fixed external feedback maintains low  
drift for critical QPI applications. In bypass mode, the 9ZX21901  
can provide outputs up to 400MHz.  
Fixed feedback path/ 0ps input-to-output delay  
9 Selectable SMBus addresses/ Multiple devices can  
share same SMBus segment  
8 dedicated OE# pins/ hardware control of outputs  
PLL or bypass mode/ PLL can dejitter incoming clock  
Selectable PLL BW/ minimizes jitter peaking in  
downstream PLL's  
Recommended Application  
19 output PCIe Gen3/QPI buffer with fixed feedback for Romley  
platforms  
Spread spectrum compatible/tracks spreading input clock  
for EMI reduction  
Output Features  
SMBus Interface/ unused outputs can be disabled  
100MHz & 133.33MHz PLL mode/ Legacy QPI support  
Undriven differential outputs in Power Down mode for  
maximum power savings  
19 - 0.7V current mode differential HCSL output pairs  
Key Specifications  
Cycle-to-cycle jitter: < 50ps  
Output-to-output skew: <65ps  
Input-to-output delay: Fixed at 0 ps  
Input-to-output delay variation: <50ps  
Phase jitter: PCIe Gen3 < 1ps rms  
Phase jitter: QPI 9.6GB/s < 0.2ps rms  
Functional Block Diagram  
8
OE(5_12)#  
DFB_OUT  
Z-PLL  
(SS Compatible)  
DIF(18:0)  
DIF_IN  
DIF_IN#  
HIBW_BYPM_LOBW#  
100M_133M#  
CKPWRGD/PD#  
SMB_A0_tri  
SMB_A1_tri  
Logic  
SMBDAT  
SMBCLK  
IREF  
Note: Even though the feedback is fixed, DFB_OUT still needs a  
termination network for the part to function.  
IDT® 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
1648H - 12/08/11  
1

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