DATASHEET
ICS9P936
Low Skew Dual Bank DDR I/II Fan-out Buffer
Description
Pin Configuration
Dual DDR I/II fanout buffer for VIA Chipset
AVDD2.5
AGND
GND
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDDQ2.5/1.8
Output Features
BUF_INT
BUF_INC
DDRT0
DDRC0
DDRT1
DDRC1
AVDD2.5
AGND
3
•
Low skew, fanout buffer
4
•
•
•
SMBus for functional and output control
Single bank 1-6 differential clock distribution
1 pair of differential feedback pins for input to output
synchronization
DDRT5
DDRC5
5
6
GND
7
•
•
•
•
Supports up to 2 DDR DIMMs
VDDQ2.5/1.8
DDRT4
8
266MHz (DDRI 533) output frequency support
400MHz (DDRII 800) output frequency support
Programmable skew through SMBus
GND
9
VDDQ2.5/1.8
DDRC4
DDRT3
10
11
12
13
14
FB_OUTT
FB_OUTC
DDRT2
•
Individual output control programmable through SMBus
DDRC3
SDATA
SCLK
DDRC2
Key Specifications
28-SSOP & TSSOP
•
•
•
•
OUTPUT - OUTPUT skew: <100ps
Output Rise and Fall Time for DDR outputs: 650ps - 950ps
DUTY CYCLE: 47% - 53%
28-pin SSOP/TSSOP package
•
RoHS compliant packaging
Funtional Block Diagram
BUF_INC
BUF_INT
Control
Logic
SCLK
FB_OUTC
FB_OUTT
SDATA
DDRC (5:0)
DDRT (5:0)
IDTTM/ICSTM Low Skew Dual Bank DDR I/II Fan-out Buffer
1084C 12/03/09