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9LPRS525AGILF PDF预览

9LPRS525AGILF

更新时间: 2024-01-12 00:27:31
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
21页 235K
描述
TSSOP-56, Tube

9LPRS525AGILF 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:TSSOP
包装说明:6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-56针数:56
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.3
Samacsys Confidence:3Samacsys Status:Released
2D Presentation:https://componentsearchengine.com/2D/0T/1284768.2.1.pngSchematic Symbol:https://componentsearchengine.com/symbol.php?partID=1284768
PCB Footprint:https://componentsearchengine.com/footprint.php?partID=12847683D View:https://componentsearchengine.com/viewer/3D.php?partID=1284768
Samacsys PartID:1284768Samacsys Image:https://componentsearchengine.com/Images/9/9LPRS525AGLF.jpg
Samacsys Thumbnail Image:https://componentsearchengine.com/Thumbnails/2/9LPRS525AGLF.jpgSamacsys Pin Count:56
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Small Outline Packages
Samacsys Footprint Name:PAG56_Samacsys Released Date:2020-01-17 12:09:31
Is Samacsys:NJESD-30 代码:R-PDSO-G56
JESD-609代码:e3长度:14 mm
湿度敏感等级:1端子数量:56
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP56,.3,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Clock Generators
最大压摆率:200 mA最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:6.1 mmuPs/uCs/外围集成电路类型:MICROPROCESSOR CIRCUIT
Base Number Matches:1

9LPRS525AGILF 数据手册

 浏览型号9LPRS525AGILF的Datasheet PDF文件第2页浏览型号9LPRS525AGILF的Datasheet PDF文件第3页浏览型号9LPRS525AGILF的Datasheet PDF文件第4页浏览型号9LPRS525AGILF的Datasheet PDF文件第5页浏览型号9LPRS525AGILF的Datasheet PDF文件第6页浏览型号9LPRS525AGILF的Datasheet PDF文件第7页 
DATASHEET  
56-pin CK505 for Intel Systems  
ICS9LPRS525  
Recommended Application:  
56-pin CK505 compatible clock, w/fully integrated Vreg and series Features/Benefits:  
resistors on differential outputs  
Supports spread spectrum modulation, 0 to -0.5% down  
spread  
Output Features:  
Supports CPU clks up to 400MHz  
Uses external 14.318MHz crystal, external crystal load  
caps are required for frequency tuning  
2 - CPU differential low power push-pull pairs  
7 - SRC differential push-pull pairs  
1 - CPU/SRC selectable differential low power push-pull pair  
1 - SRC/DOT selectable differential low power push-pull pair  
1 - SRC/SE selectable differential push-pull pair/Single-ended  
outputs  
Table 1: CPU Frequency Select Table  
FSLC2 FSLB1 FSLA1  
CPU  
MHz  
SRC  
MHz  
PCI  
REF USB DOT  
MHz MHz MHz MHz  
B0b7  
B0b6  
B0b5  
5 - PCI, 33MHz  
1 - USB, 48MHz  
1 - REF, 14.318MHz  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
266.66  
133.33  
200.00  
166.66  
333.33  
100.00  
400.00  
100.00 33.33 14.318 48.00 96.00  
Key Specifications:  
CPU outputs cycle-cycle jitter < 85ps  
SRC output cycle-cycle jitter < 125ps  
PCI outputs cycle-cycle jitter < 250ps  
+/- 100ppm frequency accuracy on all outputs  
SRC outputs meet PCIe Gen2 when sourced from PLL3  
Reserved  
1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in  
the Input/Supply/Common Output Parameters Table for correct values.  
Also refer to the Test Clarification Table.  
2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS  
specifications in the Input/Supply/Common Output Parameters Table for correct values.  
Pin Configuration  
PCI0/CR#_A 1  
56 SCLK  
VDDPCI 2  
PCI1/CR#_B 3  
PCI2/TME 4  
55 SDATA  
54 REF0/FSLC/TEST_SEL  
53 VDDREF  
PCI3/CFG0 5  
52 X1  
PCI4/SRC5_EN 6  
PCI_F5/ITP_EN 7  
GNDPCI 8  
VDD48 9  
USB_48MHz/FSLA 10  
GND48 11  
51 X2  
50 GNDREF  
49 FSLB/TEST_MODE  
48 CK_PWRGD/PD#  
47 VDDCPU  
46 CPUT0_LRS  
VDD96IO 12  
45 CPUC0_LRS  
DOTT_96_LRS/SRCT0_LRS 13  
DOTC_96_LRS/SRCC0_LRS 14  
GND 15  
44 GNDCPU  
43 CPUT1_F_LRS  
42 CPUC1_F_LRS  
41 VDDCPUIO  
VDD 16  
SRCT1_LRS/SE1 17  
SRCC1_LRS/SE2 18  
GND 19  
40 NC  
39 CPUT2_ITP_LRS/SRCT8_LRS  
38 CPUC2_ITP_LRS/SRCC8_LRS  
37 VDDSRCIO  
VDDPLL3IO 20  
SRCT2_LRS/SATAT_LRS 21  
SRCC2_LRS/SATAC_LRS 22  
GNDSRC 23  
36 SRCT7_LRS/CR#_F  
35 SRCC7_LRS/CR#_E  
34 GNDSRC  
SRCT3_LRS/CR#_C 24  
SRCC3_LRS/CR#_D 25  
VDDSRCIO 26  
33 SRCT6_LRS  
32 SRCC6_LRS  
31 VDDSRC  
SRCT4_LRS 27  
SRCC4_LRS 28  
30 PCI_STOP#/SRCT5_LRS  
29 CPU_STOP#/SRCC5_LRS  
56-SSOP & TSSOP  
IDTTM/ICSTM PC MAIN CLOCK  
1484A—04/28/09  
1

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