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9LPR502YFLFT

更新时间: 2024-01-20 02:00:07
品牌 Logo 应用领域
艾迪悌 - IDT 稳压器微控制器和处理器外围集成电路uCs集成电路uPs集成电路光电二极管
页数 文件大小 规格书
29页 283K
描述
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR

9LPR502YFLFT 技术参数

生命周期:Active包装说明:,
Reach Compliance Code:compliant风险等级:5.63
uPs/uCs/外围集成电路类型:MICROPROCESSOR CIRCUITBase Number Matches:1

9LPR502YFLFT 数据手册

 浏览型号9LPR502YFLFT的Datasheet PDF文件第2页浏览型号9LPR502YFLFT的Datasheet PDF文件第3页浏览型号9LPR502YFLFT的Datasheet PDF文件第4页浏览型号9LPR502YFLFT的Datasheet PDF文件第5页浏览型号9LPR502YFLFT的Datasheet PDF文件第6页浏览型号9LPR502YFLFT的Datasheet PDF文件第7页 
Datasheet  
ICS9LPR502  
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE  
REGULATOR  
Recommended Application:  
CK505 compliant clock with fully integrated voltage  
regulator, PCIe Gen 1 compliant  
Key Specifications:  
CPU outputs cycle-cycle jitter < 85ps  
SRC output cycle-cycle jitter < 125ps  
PCI outputs cycle-cycle jitter < 250ps  
Output Features:  
+/- 100ppm frequency accuracy on CPU & SRC  
clocks  
2 - CPU differential low power push-pull pairs  
7 - SRC differential low power push-pull pairs  
Features/Benefits:  
1 - CPU/SRC selectable differential low power push-pull  
pair  
Does not require external pass transistor for voltage  
regulator  
1 - SRC/DOT selectable differential low power push-pull  
pair  
Supports spread spectrum modulation, default is 0.5%  
down spread  
5 - PCI, 33MHz  
Uses external 14.318MHz crystal, external crystal  
load caps are required for frequency tuning  
1 - PCI_F, 33MHz free running  
1 - USB, 48MHz  
One differential push-pull pair selectable between  
SRC and two single-ended outputs  
1 - REF, 14.318MHz  
Table 1: CPU Frequency Select Table  
Pin Configuration  
FSLC2 FSLB1 FSLA1  
PCI0/CR#_A 1  
56 SCLK  
55 SDATA  
54 REF0/FSLC/TEST_SEL  
53 VDDREF  
52 X1  
51 X2  
50 GNDREF  
49 FSLB/TEST_MODE  
48 CK_PWRGD/PD#  
47 VDDCPU  
CPU  
MHz  
SRC  
MHz  
PCI  
MHz  
REF  
MHz  
USB  
MHz  
DOT  
MHz  
VDDPCI 2  
B0b7  
B0b6  
B0b5  
PCI1/CR#_B 3  
PCI2/TME 4  
PCI3 5  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
266.66  
133.33  
200.00  
166.66  
333.33  
100.00  
400.00  
100.00  
33.33 14.318 48.00  
Reserved  
96.00  
PCI4/SRC5_EN 6  
PCI_F5/ITP_EN 7  
GNDPCI 8  
VDD48 9  
USB_48MHz/FSLA 10  
GND48 11  
VDDI/O96Mhz 12  
DOTT_96/SRCT0 13  
DOTC_96/SRCC0 14  
GND 15  
1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in  
the Input/Supply/Common Output Parameters Table for correct values.  
Also refer to the Test Clarification Table.  
46 CPUT0  
45 CPUC0  
44 GNDCPU  
43 CPUT1  
2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS  
specifications in the Input/Supply/Common Output Parameters Table for correct values.  
42 CPUC1  
VDD 16  
41 VDDI/OCPU  
40 NC  
17  
SRCT1/SE1  
SRCC1/SE2 18  
GND 19  
VDDPLL3I/O 20  
SRCT2/SATAT 21  
SRCC2/SATAC 22  
GNDSRC 23  
39 CPUT2_ITP/SRCT8  
38 CPUC2_ITP/SRCC8  
37 VDDSRCI/O  
36 SRCT7/CR#_F  
35 SRCC7/CR#_E  
34 GNDSRC  
SRCT3/CR#_C 24  
SRCC3/CR#_D 25  
VDDSRCI/O 26  
SRCT4 27  
33 SRCT6  
32 SRCC6  
31 VDDSRC  
30 PCI_STOP#/SRCT5  
29 CPU_STOP#/SRCC5  
SRCC4 28  
56-SSOP/TSSOP  
IDTTM/ICSTM 56-pin CK505 w/Fully Integrated Voltage Regulator  
1124D—02/26/09  
1

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