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9DB633AFLF PDF预览

9DB633AFLF

更新时间: 2024-01-10 07:43:07
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器逻辑集成电路光电二极管PC
页数 文件大小 规格书
14页 237K
描述
Six Output Differential Buffer for PCIe Gen3

9DB633AFLF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP, TSSOP28,.25针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.54
系列:9DB输入调节:DIFFERENTIAL
JESD-30 代码:R-PDSO-G28JESD-609代码:e3
长度:9.7 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:28
实输出次数:6最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP28,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.05 ns座面最大高度:1.2 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
Base Number Matches:1

9DB633AFLF 数据手册

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DATASHEET  
Six Output Differential Buffer for PCIe Gen3  
9DB633  
Features/Benefits:  
Recommended Application:  
OE# pins/Suitable for Express Card applications  
6 output PCIe Gen3 zero-delay/fanout buffer  
PLL or bypass mode/PLL can dejitter incoming clock  
Selectable PLL bandwidth/minimizes jitter peaking in  
downstream PLL's  
General Description:  
The 9DB633 zero-delay buffer supports PCIe Gen3  
requirements, while being backwards compatible to PCIe  
Gen2 and Gen1. The 9DB633 is driven by a differential SRC  
output pair from an IDT 932S421 or 932SQ420 or equivalent  
main clock generator. It attenuates jitter on the input clock  
and has a selectable PLL bandwidth to maximize  
performance in systems with or without Spread-Spectrum  
clocking. An SMBus interface allows control of the PLL  
bandwidth and bypass options, while 2 clock request (OE#)  
pins make the 9DB633 suitable for Express Card  
applications.  
Spread Spectrum Compatible/tracks spreading input  
clock for low EMI  
SMBus Interface/unused outputs can be disabled  
Output Features:  
6 - 0.7V current mode differential HCSL output pairs  
Key Specifications:  
Cycle-to-cycle jitter < 50 ps  
Output-to-output skew < 50 ps  
PCIe Gen3 phase jitter < 1.0ps RMS  
Block Diagram  
OE1#  
OE4#  
DIF1  
SRC_IN  
SPREAD  
COMPATIBLE  
PLL  
SRC_IN#  
DIF4  
DIF(0,2,3,5)  
PLL_BW  
SMBDAT  
SMBCLK  
CONTROL  
LOGIC  
IREF  
IDT® Six Output Differential Buffer for PCIe Gen3  
1668C—04/20/11  
1

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