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9DB423BGLF PDF预览

9DB423BGLF

更新时间: 2024-02-28 14:43:00
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器逻辑集成电路光电二极管PC
页数 文件大小 规格书
19页 282K
描述
Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI

9DB423BGLF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP-28针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.82
系列:9DB输入调节:DIFFERENTIAL MUX
JESD-30 代码:R-PDSO-G28JESD-609代码:e3
长度:9.7 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:28
实输出次数:4最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP28,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.05 ns座面最大高度:1.2 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
Base Number Matches:1

9DB423BGLF 数据手册

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DATASHEET  
9DB423B  
Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI  
Recommended Application:  
DB400Q compatible part with PCIe Gen1, Gen 2 and QPI  
support  
Features/Benefits  
Spread spectrum modulation tolerant, 0 to -0.5% down  
spread and +/- 0.25% center spread.  
Supports undriven differential outputs in Power Down and  
DIF_STOP# modes for power management.  
General Description:  
The ICS9DB423 is compatible with the Intel DB400Q Differential  
Buffer Specification. This buffer provides 4 PCI-Express SRC or  
4 QPI clocks. The ICS9DB423 is driven by a differential output  
pair from a CK410B+ or CK509B main clock generator.  
Output Features  
4 - 0.7V current-mode differential output pairs  
Supports zero delay buffer mode and fanout mode  
Bandwidth programming available  
Key Specifications  
Output cycle-cycle jitter < 50ps.  
Output to Output skew <50ps  
Phase jitter: PCIe Gen1 < 86ps peak to peak  
Phase jitter: PCIe Gen2 < 3.0/3.1ps rms  
Phase jitter: QPI < 0.5ps rms  
50-133 MHz operation in PLL mode  
33-400 MHz operation in Bypass mode  
RoHS compliant packaging  
Funtional Block Diagram  
2
OE(6,1)  
SPREAD  
COMPATIBLE  
PLL  
SRC_IN  
SRC_IN#  
4
M
U
X
STOP  
DIF(6,5,2,1)  
LOGIC  
PD  
BYPASS#_133_100  
HIGH_BW#  
DIF_STOP#  
SDATA  
SCLK  
CONTROL  
LOGIC  
IREF  
Note: Polarities shown for OE_INV = 0.  
IDT® Four Output Differential Buffer for PCIe and Gen 1, Gen 2 and QPI  
1437B - 02/04/10  
1

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