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9DB1233AGLFT PDF预览

9DB1233AGLFT

更新时间: 2024-02-10 06:01:49
品牌 Logo 应用领域
艾迪悌 - IDT PC
页数 文件大小 规格书
15页 185K
描述
Twelve Output Differential Buffer for PCIe Gen3

9DB1233AGLFT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP, TSSOP64,.32,20针数:64
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.44
系列:9DB输入调节:DIFFERENTIAL MUX
JESD-30 代码:R-PDSO-G64JESD-609代码:e3
长度:17 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:64
实输出次数:12最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP64,.32,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.05 ns座面最大高度:1.2 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:6.1 mm
Base Number Matches:1

9DB1233AGLFT 数据手册

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DATASHEET  
Twelve Output Differential Buffer for PCIe Gen3  
9DB1233  
Recommended Application  
Features/Benefits  
3 Selectable SMBus Addresses/Mulitple devices can share  
the same SMBus Segment  
12 output PCIe Gen3 zero-delay/fanout buffer  
12 OE# pins/Hardware control of each output  
General Description  
PLL or bypass mode/PLL can dejitter incoming clock  
The 9DB1233 zero-delay buffer supports PCIe Gen3  
requirements, while being backwards compatible to PCIe Gen2  
and Gen1. The 9DB1233 is driven by a differential SRC output  
pair from an IDT 932S421 or 932SQ420 or equivalent main  
clock generator. It attenuates jitter on the input clock and has a  
selectable PLL bandwidth to maximize performance in systems  
with or without Spread-Spectrum clocking.  
Selectable PLL bandwidth/minimizes jitter peaking in  
downstream PLL's  
Spread Spectrum Compatible/tracks spreading input clock  
for low EMI  
SMBus Interface/unused outputs can be disabled  
Supports undriven differential outputs in Power Down mode  
for power management  
Output Features  
12 - 0.7V current mode differential HCSL output pairs  
Key Specifications  
Output cycle-cycle jitter < 50ps.  
Output-to-output skew < 50 ps  
PCIe Gen3 phase jitter < 1.0ps RMS  
Pin compatible with DB1200 Yellow Cover Device  
Functional Block Diagram  
12  
OE_(11:0)#  
SPREAD  
COMPATIBLE  
PLL  
DIF_IN  
DIF_IN#  
M
U
X
12  
DIF(11:0))  
HIGH_BW#  
BYPASS#/PLL  
VTTPWRGD#/PD  
CONTROL  
LOGIC  
ADR_SEL  
SMBDAT  
SMBCLK  
IREF  
IDT® Twelve Output Differential Buffer for PCIe Gen3  
1675B—11/08/10  
1

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