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9DB102BGLF PDF预览

9DB102BGLF

更新时间: 2024-01-28 17:32:47
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器逻辑集成电路光电二极管PC
页数 文件大小 规格书
13页 186K
描述
Two Output Differential Buffer for PCIe Gen1 & Gen2

9DB102BGLF 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:TSSOP, TSSOP20,.25Reach Compliance Code:compliant
风险等级:5.84JESD-30 代码:R-PDSO-G20
JESD-609代码:e3湿度敏感等级:1
端子数量:20最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源:3.3 V认证状态:Not Qualified
子类别:Clock Drivers标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
Base Number Matches:1

9DB102BGLF 数据手册

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DATASHEET  
ICS9DB102  
Two Output Differential Buffer for PCIe Gen1 & Gen2  
Description  
Features/Benefits  
The ICS9DB102 zero-delay buffer supports PCI Express  
clocking requirements. The ICS9DB102 is driven by a differential  
SRC output pair from an ICS CK410/CK505-compliant main  
clock. It attenuates jitter on the input clock and has a selectable  
PLL Band Width to maximize performance in systems with or  
without Spread-Spectrum clocking.  
CLKREQ# pin for outputs 1 and 4/output enable for Express  
Card applications  
PLL or bypass mode/PLL can dejitter incoming clock  
Selectable PLL bandwidth/minimizes jitter peaking in  
downstream PLLs  
Spread Spectrum Compatible/tracks spreading input clock  
for low EMI  
SMBus Interface/unused outputs can be disabled  
Industrial temperature range available  
Output Features  
2 - 0.7V current mode differential output pairs (HCSL)  
Key Specifications  
Cycle-to-cycle jitter < 35ps  
Output-to-output skew < 25ps  
Functional Block Diagram  
CLKREQ0#  
CLKREQ1#  
PCIEX0  
PCIEX1  
CLK_INT  
SPREAD  
COMPATIBLE  
PLL  
CLK_INC  
PLL_BW  
SMBDAT  
SMBCLK  
CONTROL  
LOGIC  
IREF  
IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2  
852 REV K 04/01/10  
1

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