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89TSF552BL

更新时间： 2024-02-25 11:12:18

品牌	Logo	应用领域
艾迪悌 - IDT		微控制器和处理器外围集成电路 uCs集成电路 uPs集成电路
页数	文件大小	规格书
30页	376K
描述
Traffic Manager Co-processor

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89TSF552BL 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	BGA
包装说明：	35 X 35 MM, 1 MM PITCH, FPBGA-960	针数：	960
Reach Compliance Code：	compliant	HTS代码：	8542.31.00.01
风险等级：	5.71	Is Samacsys：	N
JESD-30 代码：	S-PBGA-B960	JESD-609代码：	e0
长度：	35 mm	端子数量：	960
最高工作温度：	85 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装形状：	SQUARE	封装形式：	GRID ARRAY
峰值回流温度（摄氏度）：	225	认证状态：	Not Qualified
座面最大高度：	3.29 mm	最大供电电压：	1.89 V
最小供电电压：	1.71 V	标称供电电压：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	OTHER	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	30	宽度：	35 mm
uPs/uCs/外围集成电路类型：	MICROPROCESSOR CIRCUIT	Base Number Matches：	1

89TSF552BL 数据手册

89TTM553

Preliminary Information*

Traffic Manager Co-processor

Data Sheet

Description

89TTM55x Features

◆

Deterministic performance at 10 Gbps wire-speed (35 Mcps)

regardless of the number of flows, traffic size, and patterns.

The 89TTM553 is a flow-based traffic management co-processor

that can be used in conjunction with the 89TTM552.

Up to 256 megabytes of external memory buffer space

(equivalent to a 210 ms buffer at 10 Gbps).

It has two major functional parts: the queue manager (QM) and the

FLQ scheduler. The QM is responsible for all the non-bandwidth func-

tions, which include managing up to 1 Million queuing structures,

handling cell and packet arrivals and departures from these queues, and

maintaining a database of congestion management and statistics

parameters for each flow queue (FLQ). The FLQ scheduler is respon-

sible for managing the FLQ bandwidth functions.

Support (Rx and Tx) for industry-standard SPI-4 phase 2,

NPF Streaming Interface, and CSIX over LVDS.

Hierarchical queuing and precise scheduling:

–

Traffic management flexibility.

Support for up to 4K aggregate flow queues (AFQs), 1K port

queues (PQs), 2K arrival reassembly queues (ARQs), and 1K

output queues/channels (OQs) with no external memory

required. Configurable AFQ-to-port assignments.

Support for up to 1M discrete flows (FLQs), with queuing for

each flow, using external memory. Configurable mapping of

FLQs into aggregate flow queues.

Two-level FLQ scheduling mode that supports up to 128K or

256K virtual pipe or subscriber queues with up to 8 or 4 CoS

priority queues each.

The 89TTM553 FLQ scheduler supports traffic scheduling on up to

1M discrete flows. In addition to the scheduling levels provided by the

89TTM552, the 89TTM553 provides one or two levels of additional

scheduling hierarchy. It also provides guaranteed minimum rate,

maximum rate capping, excess rate distribution using weighted fair

queuing (WFQ), byte rate shaping, and dynamic configuration adjust-

ments.

–

The 89TTM553 stores all the flow-based parameters (and state infor-

mation) that are made available to the 89TTM552 for flow-based

processing. When the 89TTM553 is used with the 89TTM552, conges-

tion and bandwidth management features are enabled at the flow level

as well as at the aggregate-flow level.

Accurate byte-rate shaping at the FLQ, AFQ and port levels.

◆

Multiple levels of buffer congestion management.

–

Hierarchical queue structure and thresholding.

Congestion indication.

Dynamic adjustment of thresholds during periods of congestion.

Packet discard (PD).

Weighted random early discard (WRED).

Local congestion indication (CI).

–

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.

1 of 30

March 3, 2005

DSC 6797

 2005 Integrated Device Technology, Inc.

*Notice: The information in this document is subject to change without notice

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