89PES32T8
Product Brief
32-Lane 8-Port PCI Express®
Switch
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Legacy Support
Device Overview
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PCI compatible INTx emulation
Bus locking
The 89HPES32T8 is a member of the IDT PRECISE™ family of PCI
Express® switching solutions. The PES32T8 is a 32-lane, 8-port periph-
eral chip that performs PCI Express Packet switching with a feature set
optimized for high performance applications such as servers, storage,
and communications/networking. It provides connectivity and switching
functions between a PCI Express upstream port and up to seven down-
stream ports and supports switching between downstream ports.
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Highly Integrated Solution
Requires no external components
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Incorporates on-chip internal memory for packet buffering and
queueing
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Integrates thirty-two 2.5 Gbps embedded SerDes with 8B/10B
encoder/decoder (no separate transceivers needed)
Features
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Reliability, Availability, and Serviceability (RAS) Features
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High Performance PCI Express Switch
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Supports ECRC and Advanced Error Reporting
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Thirty-two 2.5 Gbps PCI Express lanes
Eight switch ports
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Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
Upstream port configurable up to x8
Downstream ports configurable up to x8
Low-latency cut-through switch architecture
Support for Max Payload Size up to 2048 bytes
One virtual channel
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Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
Compatible with Hot-Plug I/O expanders used on PC and
server motherboards
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Power Management
Eight traffic classes
PCI Express Base Specification Revision 1.1 compliant
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Utilizes advanced low-power design techniques to achieve low
typical power consumption
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Flexible Architecture with Numerous Configuration Options
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Supports PCI Power Management Interface specification
(PCI-PM 1.1)
• Supports device power management states: D0, D3hot and
D3cold
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Automatic per port link width negotiation to x8, x4, x2 or x1
Automatic lane reversal on all ports
Automatic polarity inversion on all lanes
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Unused SerDes are disabled
Ability to load device configuration from serial EEPROM
Block Diagram
8-Port Switch Core / 32 PCI Express Lanes
Port
Frame Buffer
Route Table
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Transaction Layer
Data Link Layer
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Multiplexer / Demultiplexer
Multiplexer / Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
SerDes SerDes
SerDes
SerDes SerDes
SerDes
SerDes SerDes
SerDes
SerDes
SerDes
SerDes
(Port 1)
Figure 1 Internal Block Diagram
(Port 7)
(Port 0)
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
1 of 2
February 8, 2007
© 2007 Integrated Device Technology, Inc.
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