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89PES12N3 PDF预览

89PES12N3

更新时间: 2024-02-10 11:17:40
品牌 Logo 应用领域
艾迪悌 - IDT 开关微控制器和处理器外围集成电路uCs集成电路uPs集成电路PC
页数 文件大小 规格书
2页 54K
描述
12 Lane 3-Port PCI Express㈢ Switch

89PES12N3 技术参数

生命周期:Obsolete包装说明:,
Reach Compliance Code:compliant风险等级:5.84
Is Samacsys:NBase Number Matches:1

89PES12N3 数据手册

 浏览型号89PES12N3的Datasheet PDF文件第2页 
89PES12N3  
12 Lane 3-Port PCI Express® Switch  
Product Brief  
Highly Integrated Solution  
– Requires no external components  
Device Overview  
The PES12N3, a 12 lane 3-port PCI Express® switch, is a member  
of IDT’s PRECISE™ family of PCI Express switching solutions. The  
PES12N3 is a peripheral chip that performs PCI Express Base switching  
with a feature set optimized for high performance applications such as  
servers and storage. It provides connectivity and switching functions  
between a PCI Express upstream port and two downstream ports or  
peer-to-peer switching between downstream ports.  
– Incorporates on-chip internal memory for packet buffering and  
queueing  
– Integrates 12 2.5 Gbps embedded SerDes, 8B/10B encoder/  
decoder (no separate transceivers needed)  
Reliability, Availability, and Serviceability (RAS) Features  
– Internal end-to-end parity protection on all TLPs ensures data  
integrity even in systems that do not implement end-to-end  
CRC (ECRC)  
Features  
– Supports ECRC passed through  
– Supports PCI Express Native Hot-Plug  
High Performance PCI Express Switch  
– Three x4 ports with 12 PCI lanes total  
• Compatible with Hot-Plug I/O expanders used on PC moth-  
erboards  
– Supports Hot-Swap  
Power Management  
– Supports PCI Express Power Management Interface Specifi-  
cation, Revision 1.1 (PCI-PM)  
– Delivers 6 GBps (48 Gbps) aggregate switching capacity  
– Low latency cut-through switch architecture  
– Supports 128 to 256 byte maximum payload size  
– Supports one virtual channel  
– PCI Express Base specification Revision 1.0a compliant  
Flexible Architecture with Numerous Configuration Options  
– Unused SerDes are disabled  
– Port arbitration schemes utilizing round robin or weighted  
round robin algorithms  
– Supports automatic per port link with negotiation (x4, x2, or x1)  
– Supports static lane reversal on all ports  
– Supports polarity inversion  
– Supports Advanced Configuration and Power Interface Speci-  
fication, Revision 2.0 (ACPI) supporting active link state  
Testability and Debug Features  
– Supports IEEE 1149.6 JTAG  
– Built in SerDes Pseudo-Random Bit Stream (PRBS) generator  
– Ability to read and write any internal register via the SMBus  
– Ability to bypass link training and force any link into any mode  
– Provides statistics and performance counters  
– Supports locked transactions, allowing use with legacy soft-  
ware  
– Ability to load device configuration from serial EEPROM  
Block Diagram  
3-Port Switch Core  
Port  
Arbitration  
Scheduler  
Route Table  
Frame Buffer  
Transaction Layer  
Transaction Layer  
Data Link Layer  
Transaction Layer  
Data Link Layer  
Data Link Layer  
Multiplexer/Demultiplexer  
Multiplexer/Demultiplexer  
Multiplexer/Demultiplexer  
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SerDes  
SerDes  
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SerDes SerDes  
SerDes  
SerDes SerDes  
SerDes  
SerDes  
SerDes  
12 PCI Express Lanes  
One x4 Upstream Port and Two x4 Downstream Ports  
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.  
1 of 2  
February 15, 2006  
DSC 6801  
© 2006 Integrated Device Technology, Inc.  

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