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87972DYILF PDF预览

87972DYILF

更新时间: 2024-02-22 11:56:39
品牌 Logo 应用领域
艾迪悌 - IDT 晶体时钟发生器微控制器和处理器外围集成电路
页数 文件大小 规格书
17页 161K
描述
LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER

87972DYILF 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:10 X 10 MM, 1.40 MM HEIGHT, MS-026BCC, LQFP-52针数:52
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
JESD-30 代码:S-PQFP-G52JESD-609代码:e0
长度:10 mm湿度敏感等级:3
端子数量:52最高工作温度:85 °C
最低工作温度:-40 °C最大输出时钟频率:125 MHz
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP52,.47SQ封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):240
电源:3.3 V主时钟/晶体标称频率:25 MHz
认证状态:Not Qualified座面最大高度:1.6 mm
子类别:Clock Generators最大压摆率:250 mA
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:10 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

87972DYILF 数据手册

 浏览型号87972DYILF的Datasheet PDF文件第2页浏览型号87972DYILF的Datasheet PDF文件第3页浏览型号87972DYILF的Datasheet PDF文件第4页浏览型号87972DYILF的Datasheet PDF文件第5页浏览型号87972DYILF的Datasheet PDF文件第6页浏览型号87972DYILF的Datasheet PDF文件第7页 
ICS87972I  
LOW SKEW, 1-TO-12  
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER  
GENERAL DESCRIPTION  
FEATURES  
The ICS87972I is a low skew, LVCMOS/LVTTL Clock  
Generator. The ICS87972I has three selectable inputs  
and provides fourteen LVCMOS/LVTTL outputs.  
Fully integrated PLL  
Fourteen LVCMOS/LVTTL outputs; (12) clocks,  
(1) feedback, (1) sync  
The ICS87972I is a highly flexible device. Using the crystal  
oscillator input, it can be used to generate clocks for a  
system. All of these clocks can be the same frequency or  
the device can be configured to generate up to three  
different frequencies among the three output banks. Using  
one of the single ended inputs, the ICS87972I can be  
used as a zero delay buffer/multiplier/divider in clock  
distribution applications.  
Selectable crystal oscillator interface or LVCMOS/LVTTL  
reference clock inputs  
CLK0, CLK1 can accept the following input levels:  
LVCMOS or LVTTL  
Output frequency range: 8.33MHz to 125MHz  
VCO range: 200MHz to 480MHz  
Output skew: 550ps (maximum)  
The three output banks and feedback output each have their  
own output dividers which allows the device to generate a  
multitude of different bank frequency ratios and output-to-  
input frequency ratios. In addition, 2 outputs in Bank C (QC2,  
QC3) can be selected to be inverting or non-inverting.  
The output frequency range is 8.33MHz to125MHz. Input  
frequency range is 5MHz to 120MHz.  
Cycle-to-cycle jitter: 100ps (typical)  
Full 3.3V supply voltage  
-40°C to 85°C ambient operating temperature  
Available in both standard andd lead-free RoHS-compliant  
packages  
Compatible with PowerPCandPentium™ Microprocessors  
The ICS87972I also has a QSYNC output which can be used  
for system synchronization purposes. It monitors Bank A and  
Bank C outputs and goes low one period of the faster clock  
prior to coincident rising edges of Bank A and Bank C clocks.  
QSYNC then goes high again when the coincident rising  
edges of Bank A and Bank C occur. This feature is used  
primarily in applications where Bank A and Bank C are  
running at different frequencies, and is particularly useful  
when they are running at non-integer multiples of one  
another.  
PIN ASSIGNMENT  
39 38 37 36 35 34 33 32 31 30 29 28 27  
FSEL_B1  
FSEL_B0  
FSEL_A1  
FSEL_A0  
QA3  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
FSEL_FB1  
QSYNC  
GNDO  
QC0  
Example Applications:  
1. System Clock generator: Use a 16.66MHz Crystal to  
generate eight 33.33MHz copies for PCI and four  
100MHz copies for the CPU or PCI-X.  
VDDO  
VDDO  
QC1  
QA2  
FSEL_C0  
FSEL_C1  
QC2  
ICS87972I  
2. Line Card Multiplier: Multiply 19.44MHz from a back  
plane to 77.76MHz for the line Card ASICs and Serdes.  
GNDO  
QA1  
3. Zero Delay buffer for Synchronous memory: Fan out up  
to twelve 100MHz copies from a memory controller ref-  
erence clock to the memory chips on a memory module  
with zero delay.  
VDDO  
VDDO  
QA0  
QC3  
GNDO  
VCO_SEL  
GNDO  
INV_CLK  
1
2
3
4
5
6
7
8
9 10 11 12 13  
52-Lead LQFP  
10mm x 10mm x 1.4mm package body  
Y package  
TopView  
87972DYI  
www.idt.com  
REV.E JUNE 25, 2010  
1

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