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8741004AGIT PDF预览

8741004AGIT

更新时间: 2024-02-21 08:58:41
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器逻辑集成电路光电二极管衰减器PC
页数 文件大小 规格书
19页 1189K
描述
Clock Driver

8741004AGIT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:4.40 X 7.80 MM, 0.925 MM HEIGHT, TSSOP-24针数:24
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.53
系列:8741004输入调节:DIFFERENTIAL
JESD-30 代码:R-PDSO-G24JESD-609代码:e0
长度:7.8 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:24实输出次数:4
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:HTSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, HEAT SINK/SLUG, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):225认证状态:Not Qualified
座面最大高度:1.1 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
最小 fmax:98 MHzBase Number Matches:1

8741004AGIT 数据手册

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DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL  
PCI EXPRESS™ JITTER ATTENUATOR  
ICS8741004  
General Description  
Features  
The ICS8741004 is a high performance  
Differential-to-LVDS/0.7V Differential Jitter  
Attenuator designed for use in PCI Express™  
systems. In some PCI Express systems, such as  
those found in desktop PCs, the PCI Express clocks  
Two LVDS and two 0.7V differential output pairs  
Bank B has two 0.7V differential output pairs  
Bank A has two LVDS output pairs and  
S
IC  
HiPerClockS™  
One differential clock input pair  
CLK, CLK pair can accept the following differential  
are generated from a low bandwidth, high phase noise PLL  
frequency synthesizer. In these systems, a jitter attenuator may be  
required to attenuate high frequency random and deterministic  
jitter components from the PLL synthesizer and from the system  
board. The ICS8741004 has 3 PLL bandwidth modes: 200kHz,  
600kHz and 2MHz. The 200kHz mode will provide maximum jitter  
attenuation, but with higher PLL tracking skew and spread  
spectrum modulation from the motherboard synthesizer may be  
attenuated. The 600kHz provides an intermediate bandwidth that  
can easily track triangular spread profiles, while providing good  
jitter attenuation. The 2MHz bandwidth provides the best tracking  
skew and will pass most spread profiles, but the jitter attenuation  
will not be as good as the lower bandwidth modes. Because some  
2.5Gb serdes have x20 multipliers while others have x25  
multipliers, the ICS8741004 can be set for 1:1 mode or 5/4  
multiplication mode (i.e. 100MHz input/125MHz output) using the  
F_SEL pins.  
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL  
Output frequency range: 98MHz - 160MHz  
Input frequency range: 98MHz - 128MHz  
VCO range: 490MHz - 640MHz  
Cycle-to-cycle jitter: 35ps (maximum)  
Full 3.3V operating supply  
Three bandwidth modes allow the system designer to make  
jitter attenuation/tracking skew design trade-offs  
0°C to 70°C ambient operating temperature  
Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
The ICS8741004 uses IDT’s 3rd Generation FemtoClock™  
PLL technology to achieve the lowest possible phase noise.  
The device is packaged in a 24 Lead TSSOP package, making it  
ideal for use in space constrained applications such as PCI  
Express add-in cards.  
Pin Assignment  
nQB1  
QB1  
nQA1  
QA1  
1
2
24  
23  
VDDO  
QA0  
VDDO  
QB0  
3
4
22  
21  
PLL Bandwidth  
5
6
7
8
20  
19  
18  
17  
nQB0  
IREF  
F_SELB  
BW_SEL  
MR  
BW_SEL  
nc  
0 = PLL Bandwidth: ~200kHz  
Float = PLL Bandwidth: ~600kHz (default)  
1 = PLL Bandwidth: ~2MHz  
OEB  
VDDA  
GND  
GND  
nCLK  
CLK  
9
16  
15  
14  
13  
F_SELA  
VDD  
10  
11  
12  
OEA  
ICS8741004  
24-Lead TSSOP  
4.4mm x 7.8mm x 0.925mm  
package body  
G Package  
Top View  
IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR  
1
ICS8741004AG REV. ANOVEMBER 1, 2007  

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