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8705BYLFT PDF预览

8705BYLFT

更新时间: 2024-01-19 16:15:36
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器时钟发生器逻辑集成电路
页数 文件大小 规格书
18页 178K
描述
ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

8705BYLFT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP, QFP32,.35SQ,32针数:32
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.9
Is Samacsys:N其他特性:ALSO OPERATES AT 3.3V SUPPLY
系列:8705输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQFP-G32JESD-609代码:e0
长度:7 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:32
实输出次数:8最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP32,.35SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):240电源:2.5/3.3 V
Prop。Delay @ Nom-Sup:7.3 ns传播延迟(tpd):7.3 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.065 ns
座面最大高度:1.6 mm子类别:Clock Drivers
最大供电电压 (Vsup):2.625 V最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:7 mm最小 fmax:15.625 MHz
Base Number Matches:1

8705BYLFT 数据手册

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ICS8705  
ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL  
CLOCK GENERATOR  
GENERAL DESCRIPTION  
FEATURES  
The ICS8705 is a highly versatile 1:8 Differential-to- • 8 LVCMOS/LVTTL outputs, 7Ω typical output impedance  
LVCMOS/LVTTL Clock Generator. The ICS8705 has two  
• Selectable CLK1, nCLK1 or LVCMOS/LVTTL clock inputs  
selectable clock inputs. The CLK1, nCLK1 pair can accept  
• CLK1, nCLK1 pair can accept the following differential  
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL  
most standard differential input levels. The single ended  
CLK0 input accepts LVCMOS or LVTTL input levels.The  
ICS8705 has a fully integrated PLL and can be configured  
as zero delay buffer, multiplier or divider and has an input  
and output frequency range of 15.625MHz to 250MHz. The  
reference divider, feedback divider and output divider are  
each programmable, thereby allowing for the following out-  
put-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8.  
The external feedback allows the device to achieve “zero  
delay” between the input clock and the output clocks. The  
PLL_SEL pin can be used to bypass the PLL for system  
test and debug purposes. In bypass mode, the reference  
clock is routed around the PLL and into the internal output  
dividers.  
• CLK0 input accepts LVCMOS or LVTTL input levels  
• Output frequency range: 15.625MHz to 250MHz  
• Input frequency range: 15.625MHz to 250MHz  
• VCO range: 250MHz to 500MHz  
• External feedback for “zero delay” clock regeneration  
with configurable frequencies  
• Programmable dividers allow for the following output-to-input  
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8  
• Fully integrated PLL  
• Cycle-to-cycle jitter: 45ps (maximum)  
• Output skew: CLK0, 65ps (maximum)  
CLK1, nCLK1, 55ps (maximum)  
• Static Phase Offset: 25 125ps (maximum), CLK0  
• Full 3.3V or 2.5V operating supply  
• 0°C to 70°C ambient operating temperature  
• Lead-Free package fully RoHS compliant  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
PLL_SEL  
Q0  
÷2, ÷4, ÷8, ÷16,  
÷32,÷64, ÷128  
0
1
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
CLK0  
0
1
32 31 30 29 28 27 26 25  
SEL0  
SEL1  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
VDDO  
Q5  
CLK1  
nCLK1  
PLL  
CLK0  
GND  
Q4  
CLK_SEL  
8:1, 4:1, 2:1, 1:1,  
1:2, 1:4, 1:8  
nc  
FB_IN  
ICS8705  
CLK1  
VDDO  
Q3  
nCLK1  
CLK_SEL  
MR  
GND  
Q2  
9
10 11 12 13 14 15 16  
SEL0  
SEL1  
SEL2  
SEL3  
MR  
32-Lead LQFP  
7mm x 7mm x 1.4 mm  
Y Package  
Top View  
8705BY  
www.idt.com  
REV. H JULY2, 2010  
1

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