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8624BYIT PDF预览

8624BYIT

更新时间: 2024-01-11 00:41:19
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器逻辑集成电路
页数 文件大小 规格书
16页 177K
描述
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER

8624BYIT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP, QFP32,.35SQ,32针数:32
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.23
系列:8624输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQFP-G32JESD-609代码:e0
长度:7 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:32
实输出次数:5最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP32,.35SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):240电源:1.8,3.3 V
Prop。Delay @ Nom-Sup:4.4 ns传播延迟(tpd):4.4 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.025 ns
座面最大高度:1.6 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:7 mm最小 fmax:31.25 MHz
Base Number Matches:1

8624BYIT 数据手册

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ICS8624I  
LOW SKEW, 1-TO-5  
DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER  
GENERAL DESCRIPTION  
FEATURES  
The ICS8624I is  
a
high performance, 1-to-5  
Fully integrated PLL  
Differential-to-HSTL zero delay buffer. The ICS8624I  
has two selectable clock input pairs. The CLK0,  
nCLK0 and CLK1, nCLK1 pair can accept most standard  
differential input levels. The VCO operates at a frequency  
range of 250MHz to 630MHz. Utilizing one of the outputs  
as feedback to the PLL, output frequencies up to 630MHz  
can be regenerated with zero delay with respect to the  
input. Dual reference clock inputs support reduntant clock  
or multiple reference applications..  
Five differential HSTL compatible outputs  
Selectable differential CLKx, nCLKx input pairs  
CLKx, nCLKx pairs can accept the following differential  
input levels: LVPECL, LVDS, HSTL, SSTL, HCSL  
Output frequency range: 31.25MHz to 630MHz  
Input frequency range: 31.25MHz to 630MHz  
VCO range: 250MHz to 630MHz  
External feedback for “zero delay” clock regeneration  
Cycle-to-cycle jitter: 35ps (maximum)  
Output skew: 50ps (maximum)  
Static phase offset: 30ps 125ps  
3.3V core, 1.8V output operating supply  
-40°C to 85°C ambient operating temperature  
Available in both standard and lead-free RoHS-compliant  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
Q0  
nQ0  
PLL_SEL  
Q1  
nQ1  
÷4, ÷8  
0
1
32 31 30 29 28 27 26 25  
CLK0  
nCLK0  
Q2  
nQ2  
0
1
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
SEL0  
SEL1  
VDDO  
Q3  
CLK1  
nCLK1  
Q3  
nQ3  
CLK0  
nQ3  
Q2  
PLL  
nCLK0  
CLK1  
Q4  
nQ4  
CLK_SEL  
ICS8624I  
nQ2  
Q1  
nCLK1  
CLK_SEL  
MR  
FB_IN  
nFB_IN  
nQ1  
VDDO  
9
10 11 12 13 14 15 16  
SEL0  
SEL1  
MR  
32-Lead LQFP  
7mm x 7mm x 1.4mm body package  
Y Package  
TopView  
8624BYI  
www.idt.com  
REV.C JULY 30, 2010  
1

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